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c25630381c
This code was restored with commit 080fc66fb5 ("ARM: Bring back ARMv3 IO
and user access code") because the RiscPC memory bus does not understand
half-word load/stores. However only the IO code needed restoring since
the alternative user access code contains no half-word accesses, is
already used when CONFIG_PREEMPT is set and runs faster on a StrongARM.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
42 lines
1.3 KiB
Makefile
42 lines
1.3 KiB
Makefile
#
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# linux/arch/arm/lib/Makefile
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#
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# Copyright (C) 1995-2000 Russell King
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#
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lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \
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csumpartialcopy.o csumpartialcopyuser.o clearbit.o \
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delay.o delay-loop.o findbit.o memchr.o memcpy.o \
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memmove.o memset.o memzero.o setbit.o \
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strchr.o strrchr.o \
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testchangebit.o testclearbit.o testsetbit.o \
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ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \
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ucmpdi2.o lib1funcs.o div64.o \
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io-readsb.o io-writesb.o io-readsl.o io-writesl.o \
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call_with_stack.o bswapsdi2.o
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mmu-y := clear_user.o copy_page.o getuser.o putuser.o \
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copy_from_user.o copy_to_user.o
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# using lib_ here won't override already available weak symbols
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obj-$(CONFIG_UACCESS_WITH_MEMCPY) += uaccess_with_memcpy.o
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lib-$(CONFIG_MMU) += $(mmu-y)
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ifeq ($(CONFIG_CPU_32v3),y)
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lib-y += io-readsw-armv3.o io-writesw-armv3.o
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else
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lib-y += io-readsw-armv4.o io-writesw-armv4.o
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endif
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lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o
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$(obj)/csumpartialcopy.o: $(obj)/csumpartialcopygeneric.S
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$(obj)/csumpartialcopyuser.o: $(obj)/csumpartialcopygeneric.S
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ifeq ($(CONFIG_KERNEL_MODE_NEON),y)
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NEON_FLAGS := -mfloat-abi=softfp -mfpu=neon
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CFLAGS_xor-neon.o += $(NEON_FLAGS)
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obj-$(CONFIG_XOR_BLOCKS) += xor-neon.o
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endif
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