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This driver supports the Lantiq SSC SPI controller in master mode. This controller is found on Intel (former Lantiq) SoCs like the Danube, Falcon, xRX200, xRX300. The hardware uses two hardware FIFOs one for received and one for transferred bytes. When the driver writes data into the transmit FIFO the complete word is taken from the FIFO into a shift register. The data from this shift register is then written to the wire. This driver uses the interrupts signaling the status of the FIFOs and not the shift register. It is also possible to use the interrupts for the shift register, but they will send a signal after every word. When using the interrupts for the shift register we get a signal when the last word is written into the shift register and not when it is written to the wire. After all FIFOs are empty the driver busy waits till the hardware is not busy any more and returns the transfer status. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Mark Brown <broonie@kernel.org>
30 lines
810 B
Plaintext
30 lines
810 B
Plaintext
Lantiq Synchronous Serial Controller (SSC) SPI master driver
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Required properties:
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- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi"
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- #address-cells: see spi-bus.txt
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- #size-cells: see spi-bus.txt
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- reg: address and length of the spi master registers
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- interrupts: should contain the "spi_rx", "spi_tx" and "spi_err" interrupt.
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Optional properties:
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- clocks: spi clock phandle
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- num-cs: see spi-bus.txt, set to 8 if unset
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- base-cs: the number of the first chip select, set to 1 if unset.
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Example:
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spi: spi@E100800 {
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compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
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reg = <0xE100800 0x100>;
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interrupt-parent = <&icu0>;
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interrupts = <22 23 24>;
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interrupt-names = "spi_rx", "spi_tx", "spi_err";
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#address-cells = <1>;
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#size-cells = <1>;
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num-cs = <6>;
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base-cs = <1>;
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};
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