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Add clock definition and driver code for CV1800 SoC. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Link:6f4e9b8ecb/duo/datasheet/CV180X-Clock-v1.xlsxLink:6f4e9b8ecb/duo/datasheet/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdfLink: https://lore.kernel.org/r/IA1PR20MB49534F37F802CAF117364D66BB262@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
119 lines
3.5 KiB
C
119 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
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*/
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#ifndef _CLK_SOPHGO_CV1800_PLL_H_
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#define _CLK_SOPHGO_CV1800_PLL_H_
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#include "clk-cv18xx-common.h"
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struct cv1800_clk_pll_limit {
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struct {
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u8 min;
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u8 max;
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} pre_div, div, post_div, ictrl, mode;
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};
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#define _CV1800_PLL_LIMIT(_min, _max) \
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{ \
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.min = _min, \
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.max = _max, \
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} \
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#define for_each_pll_limit_range(_var, _restrict) \
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for (_var = (_restrict)->min; _var <= (_restrict)->max; _var++)
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struct cv1800_clk_pll_synthesizer {
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struct cv1800_clk_regbit en;
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struct cv1800_clk_regbit clk_half;
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u32 ctrl;
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u32 set;
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};
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#define _PLL_PRE_DIV_SEL_FIELD GENMASK(6, 0)
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#define _PLL_POST_DIV_SEL_FIELD GENMASK(14, 8)
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#define _PLL_SEL_MODE_FIELD GENMASK(16, 15)
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#define _PLL_DIV_SEL_FIELD GENMASK(23, 17)
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#define _PLL_ICTRL_FIELD GENMASK(26, 24)
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#define _PLL_ALL_FIELD_MASK \
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(_PLL_PRE_DIV_SEL_FIELD | \
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_PLL_POST_DIV_SEL_FIELD | \
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_PLL_SEL_MODE_FIELD | \
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_PLL_DIV_SEL_FIELD | \
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_PLL_ICTRL_FIELD)
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#define PLL_COPY_REG(_dest, _src) \
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(((_dest) & (~_PLL_ALL_FIELD_MASK)) | ((_src) & _PLL_ALL_FIELD_MASK))
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#define PLL_GET_PRE_DIV_SEL(_reg) \
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FIELD_GET(_PLL_PRE_DIV_SEL_FIELD, (_reg))
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#define PLL_GET_POST_DIV_SEL(_reg) \
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FIELD_GET(_PLL_POST_DIV_SEL_FIELD, (_reg))
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#define PLL_GET_SEL_MODE(_reg) \
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FIELD_GET(_PLL_SEL_MODE_FIELD, (_reg))
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#define PLL_GET_DIV_SEL(_reg) \
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FIELD_GET(_PLL_DIV_SEL_FIELD, (_reg))
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#define PLL_GET_ICTRL(_reg) \
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FIELD_GET(_PLL_ICTRL_FIELD, (_reg))
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#define PLL_SET_PRE_DIV_SEL(_reg, _val) \
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_CV1800_SET_FIELD((_reg), (_val), _PLL_PRE_DIV_SEL_FIELD)
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#define PLL_SET_POST_DIV_SEL(_reg, _val) \
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_CV1800_SET_FIELD((_reg), (_val), _PLL_POST_DIV_SEL_FIELD)
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#define PLL_SET_SEL_MODE(_reg, _val) \
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_CV1800_SET_FIELD((_reg), (_val), _PLL_SEL_MODE_FIELD)
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#define PLL_SET_DIV_SEL(_reg, _val) \
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_CV1800_SET_FIELD((_reg), (_val), _PLL_DIV_SEL_FIELD)
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#define PLL_SET_ICTRL(_reg, _val) \
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_CV1800_SET_FIELD((_reg), (_val), _PLL_ICTRL_FIELD)
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struct cv1800_clk_pll {
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struct cv1800_clk_common common;
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u32 pll_reg;
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struct cv1800_clk_regbit pll_pwd;
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struct cv1800_clk_regbit pll_status;
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const struct cv1800_clk_pll_limit *pll_limit;
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struct cv1800_clk_pll_synthesizer *pll_syn;
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};
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#define CV1800_INTEGRAL_PLL(_name, _parent, _pll_reg, \
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_pll_pwd_reg, _pll_pwd_shift, \
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_pll_status_reg, _pll_status_shift, \
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_pll_limit, _flags) \
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struct cv1800_clk_pll _name = { \
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.common = CV1800_CLK_COMMON(#_name, _parent, \
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&cv1800_clk_ipll_ops,\
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_flags), \
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.pll_reg = _pll_reg, \
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.pll_pwd = CV1800_CLK_BIT(_pll_pwd_reg, \
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_pll_pwd_shift), \
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.pll_status = CV1800_CLK_BIT(_pll_status_reg, \
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_pll_status_shift), \
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.pll_limit = _pll_limit, \
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.pll_syn = NULL, \
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}
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#define CV1800_FACTIONAL_PLL(_name, _parent, _pll_reg, \
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_pll_pwd_reg, _pll_pwd_shift, \
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_pll_status_reg, _pll_status_shift, \
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_pll_limit, _pll_syn, _flags) \
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struct cv1800_clk_pll _name = { \
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.common = CV1800_CLK_COMMON(#_name, _parent, \
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&cv1800_clk_fpll_ops,\
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_flags), \
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.pll_reg = _pll_reg, \
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.pll_pwd = CV1800_CLK_BIT(_pll_pwd_reg, \
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_pll_pwd_shift), \
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.pll_status = CV1800_CLK_BIT(_pll_status_reg, \
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_pll_status_shift), \
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.pll_limit = _pll_limit, \
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.pll_syn = _pll_syn, \
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}
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extern const struct clk_ops cv1800_clk_ipll_ops;
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extern const struct clk_ops cv1800_clk_fpll_ops;
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#endif // _CLK_SOPHGO_CV1800_PLL_H_
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