Gregory CLEMENT 6f14293257 MIPS: Allow using more than 32-bit addresses for reset vectors when possible ... While most MIPS64 CPUs use 32-bit values for their VP Local Reset Exception Base registers, some I6500 CPUs can utilize a 64-bit value, allowing addressing up to 47 bits of physical memory. For the EyeQ6H CPU, where physical memory addresses exceed the 4GB limit, utilizing this feature is mandatory to enable SMP support. Unfortunately, there is no way to detect this capability based solely on the ID of the CPU. According to Imagination, which designed the CPU, the only reliable method is to fill the reset base field with 0xFF and then read back its value. If the upper part of the read-back value is zero, it indicates that the address space is limited to 32 bits. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>		2024-10-30 23:45:48 +01:00
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asm	MIPS: Allow using more than 32-bit addresses for reset vectors when possible	2024-10-30 23:45:48 +01:00
uapi/asm	- use devm_clk_get_enabled() helper	2024-09-16 06:53:14 +02:00