Vineet Gupta a5c8b52abe ARCv2: STAR 9000837815 workaround hardware exclusive transactions livelock ... A quad core SMP build could get into hardware livelock with concurrent LLOCK/SCOND. Workaround that by adding a PREFETCHW which is serialized by SCU (System Coherency Unit). It brings the cache line in Exclusive state and makes others invalidate their lines. This gives enough time for winner to complete the LLOCK/SCOND, before others can get the line back. The prefetchw in the ll/sc loop is not nice but this is the only software workaround for current version of RTL. Cc: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2015-06-25 06:00:18 +05:30
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asm	ARCv2: STAR 9000837815 workaround hardware exclusive transactions livelock	2015-06-25 06:00:18 +05:30
uapi/asm	ARC: mm: document system mem map clearly	2015-06-19 18:09:29 +05:30