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Starting from DG2, some of the programming previously done by i915 and the GuC has been moved to the GSC and the relevant registers are no longer writable by either CPU or GuC. This is also referred to as GuC deprivilege. On the i915 side, this affects the WOPCM registers: these are no longer programmed by the driver and we do instead expect to find them already set. This can lead to verification failures because in i915 we cheat a bit with the WOPCM size defines, to keep the code common across platforms, by sometimes using a smaller WOPCM size that the actual HW support (which isn't a problem because the extra size is not needed if the FW fits in the smaller chunk), while the pre-programmed values can use the actual size. Given tha the new programming entity is trusted, relax the amount of the checks done on the pre-programmed values by not limiting the max programmed size. In the extremely unlikely scenario that the registers have been misprogrammed, we will still fail later at DMA time. v2: drop special case for DG2 G10 A0 (Alan) Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Stuart Summers <stuart.summers@intel.com> Cc: John Harrison <john.c.harrison@intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220120212947.3440448-1-daniele.ceraolospurio@intel.com
306 lines
9.7 KiB
C
306 lines
9.7 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2017-2019 Intel Corporation
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*/
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#include "intel_wopcm.h"
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#include "i915_drv.h"
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/**
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* DOC: WOPCM Layout
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*
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* The layout of the WOPCM will be fixed after writing to GuC WOPCM size and
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* offset registers whose values are calculated and determined by HuC/GuC
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* firmware size and set of hardware requirements/restrictions as shown below:
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*
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* ::
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*
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* +=========> +====================+ <== WOPCM Top
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* ^ | HW contexts RSVD |
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* | +===> +====================+ <== GuC WOPCM Top
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* | ^ | |
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* | | | |
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* | | | |
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* | GuC | |
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* | WOPCM | |
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* | Size +--------------------+
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* WOPCM | | GuC FW RSVD |
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* | | +--------------------+
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* | | | GuC Stack RSVD |
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* | | +------------------- +
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* | v | GuC WOPCM RSVD |
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* | +===> +====================+ <== GuC WOPCM base
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* | | WOPCM RSVD |
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* | +------------------- + <== HuC Firmware Top
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* v | HuC FW |
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* +=========> +====================+ <== WOPCM Base
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*
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* GuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top.
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* The top part of the WOPCM is reserved for hardware contexts (e.g. RC6
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* context).
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*/
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/* Default WOPCM size is 2MB from Gen11, 1MB on previous platforms */
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#define GEN11_WOPCM_SIZE SZ_2M
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#define GEN9_WOPCM_SIZE SZ_1M
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#define MAX_WOPCM_SIZE SZ_8M
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/* 16KB WOPCM (RSVD WOPCM) is reserved from HuC firmware top. */
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#define WOPCM_RESERVED_SIZE SZ_16K
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/* 16KB reserved at the beginning of GuC WOPCM. */
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#define GUC_WOPCM_RESERVED SZ_16K
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/* 8KB from GUC_WOPCM_RESERVED is reserved for GuC stack. */
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#define GUC_WOPCM_STACK_RESERVED SZ_8K
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/* GuC WOPCM Offset value needs to be aligned to 16KB. */
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#define GUC_WOPCM_OFFSET_ALIGNMENT (1UL << GUC_WOPCM_OFFSET_SHIFT)
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/* 24KB at the end of WOPCM is reserved for RC6 CTX on BXT. */
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#define BXT_WOPCM_RC6_CTX_RESERVED (SZ_16K + SZ_8K)
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/* 36KB WOPCM reserved at the end of WOPCM on ICL. */
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#define ICL_WOPCM_HW_CTX_RESERVED (SZ_32K + SZ_4K)
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/* 128KB from GUC_WOPCM_RESERVED is reserved for FW on Gen9. */
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#define GEN9_GUC_FW_RESERVED SZ_128K
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#define GEN9_GUC_WOPCM_OFFSET (GUC_WOPCM_RESERVED + GEN9_GUC_FW_RESERVED)
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static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
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{
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return container_of(wopcm, struct drm_i915_private, wopcm);
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}
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/**
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* intel_wopcm_init_early() - Early initialization of the WOPCM.
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* @wopcm: pointer to intel_wopcm.
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*
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* Setup the size of WOPCM which will be used by later on WOPCM partitioning.
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*/
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void intel_wopcm_init_early(struct intel_wopcm *wopcm)
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{
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struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
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if (!HAS_GT_UC(i915))
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return;
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if (GRAPHICS_VER(i915) >= 11)
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wopcm->size = GEN11_WOPCM_SIZE;
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else
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wopcm->size = GEN9_WOPCM_SIZE;
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drm_dbg(&i915->drm, "WOPCM: %uK\n", wopcm->size / 1024);
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}
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static u32 context_reserved_size(struct drm_i915_private *i915)
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{
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if (IS_GEN9_LP(i915))
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return BXT_WOPCM_RC6_CTX_RESERVED;
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else if (GRAPHICS_VER(i915) >= 11)
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return ICL_WOPCM_HW_CTX_RESERVED;
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else
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return 0;
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}
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static bool gen9_check_dword_gap(struct drm_i915_private *i915,
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u32 guc_wopcm_base, u32 guc_wopcm_size)
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{
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u32 offset;
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/*
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* GuC WOPCM size shall be at least a dword larger than the offset from
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* WOPCM base (GuC WOPCM offset from WOPCM base + GEN9_GUC_WOPCM_OFFSET)
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* due to hardware limitation on Gen9.
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*/
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offset = guc_wopcm_base + GEN9_GUC_WOPCM_OFFSET;
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if (offset > guc_wopcm_size ||
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(guc_wopcm_size - offset) < sizeof(u32)) {
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drm_err(&i915->drm,
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"WOPCM: invalid GuC region size: %uK < %uK\n",
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guc_wopcm_size / SZ_1K,
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(u32)(offset + sizeof(u32)) / SZ_1K);
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return false;
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}
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return true;
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}
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static bool gen9_check_huc_fw_fits(struct drm_i915_private *i915,
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u32 guc_wopcm_size, u32 huc_fw_size)
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{
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/*
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* On Gen9, hardware requires the total available GuC WOPCM
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* size to be larger than or equal to HuC firmware size. Otherwise,
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* firmware uploading would fail.
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*/
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if (huc_fw_size > guc_wopcm_size - GUC_WOPCM_RESERVED) {
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drm_err(&i915->drm, "WOPCM: no space for %s: %uK < %uK\n",
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intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC),
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(guc_wopcm_size - GUC_WOPCM_RESERVED) / SZ_1K,
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huc_fw_size / 1024);
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return false;
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}
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return true;
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}
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static bool check_hw_restrictions(struct drm_i915_private *i915,
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u32 guc_wopcm_base, u32 guc_wopcm_size,
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u32 huc_fw_size)
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{
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if (GRAPHICS_VER(i915) == 9 && !gen9_check_dword_gap(i915, guc_wopcm_base,
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guc_wopcm_size))
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return false;
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if (GRAPHICS_VER(i915) == 9 &&
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!gen9_check_huc_fw_fits(i915, guc_wopcm_size, huc_fw_size))
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return false;
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return true;
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}
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static bool __check_layout(struct drm_i915_private *i915, u32 wopcm_size,
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u32 guc_wopcm_base, u32 guc_wopcm_size,
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u32 guc_fw_size, u32 huc_fw_size)
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{
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const u32 ctx_rsvd = context_reserved_size(i915);
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u32 size;
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size = wopcm_size - ctx_rsvd;
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if (unlikely(range_overflows(guc_wopcm_base, guc_wopcm_size, size))) {
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drm_err(&i915->drm,
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"WOPCM: invalid GuC region layout: %uK + %uK > %uK\n",
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guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K,
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size / SZ_1K);
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return false;
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}
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size = guc_fw_size + GUC_WOPCM_RESERVED + GUC_WOPCM_STACK_RESERVED;
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if (unlikely(guc_wopcm_size < size)) {
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drm_err(&i915->drm, "WOPCM: no space for %s: %uK < %uK\n",
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intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC),
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guc_wopcm_size / SZ_1K, size / SZ_1K);
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return false;
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}
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size = huc_fw_size + WOPCM_RESERVED_SIZE;
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if (unlikely(guc_wopcm_base < size)) {
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drm_err(&i915->drm, "WOPCM: no space for %s: %uK < %uK\n",
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intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_HUC),
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guc_wopcm_base / SZ_1K, size / SZ_1K);
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return false;
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}
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return check_hw_restrictions(i915, guc_wopcm_base, guc_wopcm_size,
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huc_fw_size);
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}
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static bool __wopcm_regs_locked(struct intel_uncore *uncore,
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u32 *guc_wopcm_base, u32 *guc_wopcm_size)
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{
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u32 reg_base = intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET);
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u32 reg_size = intel_uncore_read(uncore, GUC_WOPCM_SIZE);
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if (!(reg_size & GUC_WOPCM_SIZE_LOCKED) ||
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!(reg_base & GUC_WOPCM_OFFSET_VALID))
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return false;
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*guc_wopcm_base = reg_base & GUC_WOPCM_OFFSET_MASK;
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*guc_wopcm_size = reg_size & GUC_WOPCM_SIZE_MASK;
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return true;
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}
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static bool __wopcm_regs_writable(struct intel_uncore *uncore)
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{
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if (!HAS_GUC_DEPRIVILEGE(uncore->i915))
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return true;
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return intel_uncore_read(uncore, GUC_SHIM_CONTROL2) & GUC_IS_PRIVILEGED;
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}
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/**
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* intel_wopcm_init() - Initialize the WOPCM structure.
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* @wopcm: pointer to intel_wopcm.
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*
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* This function will partition WOPCM space based on GuC and HuC firmware sizes
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* and will allocate max remaining for use by GuC. This function will also
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* enforce platform dependent hardware restrictions on GuC WOPCM offset and
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* size. It will fail the WOPCM init if any of these checks fail, so that the
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* following WOPCM registers setup and GuC firmware uploading would be aborted.
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*/
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void intel_wopcm_init(struct intel_wopcm *wopcm)
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{
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struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
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struct intel_gt *gt = to_gt(i915);
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u32 guc_fw_size = intel_uc_fw_get_upload_size(>->uc.guc.fw);
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u32 huc_fw_size = intel_uc_fw_get_upload_size(>->uc.huc.fw);
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u32 ctx_rsvd = context_reserved_size(i915);
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u32 wopcm_size = wopcm->size;
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u32 guc_wopcm_base;
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u32 guc_wopcm_size;
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if (!guc_fw_size)
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return;
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GEM_BUG_ON(!wopcm_size);
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GEM_BUG_ON(wopcm->guc.base);
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GEM_BUG_ON(wopcm->guc.size);
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GEM_BUG_ON(guc_fw_size >= wopcm_size);
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GEM_BUG_ON(huc_fw_size >= wopcm_size);
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GEM_BUG_ON(ctx_rsvd + WOPCM_RESERVED_SIZE >= wopcm_size);
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if (i915_inject_probe_failure(i915))
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return;
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if (__wopcm_regs_locked(gt->uncore, &guc_wopcm_base, &guc_wopcm_size)) {
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drm_dbg(&i915->drm, "GuC WOPCM is already locked [%uK, %uK)\n",
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guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K);
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/*
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* Note that to keep things simple (i.e. avoid different
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* defines per platform) our WOPCM math doesn't always use the
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* actual WOPCM size, but a value that is less or equal to it.
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* This is perfectly fine when i915 programs the registers, but
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* on platforms with GuC deprivilege the registers are not
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* writable from i915 and are instead pre-programmed by the
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* bios/IFWI, so there might be a mismatch of sizes.
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* Instead of handling the size difference, we trust that the
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* programmed values make sense and disable the relevant check
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* by using the maximum possible WOPCM size in the verification
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* math. In the extremely unlikely case that the registers
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* were pre-programmed with an invalid value, we will still
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* gracefully fail later during the GuC/HuC dma.
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*/
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if (!__wopcm_regs_writable(gt->uncore))
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wopcm_size = MAX_WOPCM_SIZE;
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goto check;
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}
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/*
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* Aligned value of guc_wopcm_base will determine available WOPCM space
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* for HuC firmware and mandatory reserved area.
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*/
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guc_wopcm_base = huc_fw_size + WOPCM_RESERVED_SIZE;
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guc_wopcm_base = ALIGN(guc_wopcm_base, GUC_WOPCM_OFFSET_ALIGNMENT);
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/*
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* Need to clamp guc_wopcm_base now to make sure the following math is
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* correct. Formal check of whole WOPCM layout will be done below.
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*/
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guc_wopcm_base = min(guc_wopcm_base, wopcm_size - ctx_rsvd);
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/* Aligned remainings of usable WOPCM space can be assigned to GuC. */
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guc_wopcm_size = wopcm_size - ctx_rsvd - guc_wopcm_base;
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guc_wopcm_size &= GUC_WOPCM_SIZE_MASK;
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drm_dbg(&i915->drm, "Calculated GuC WOPCM [%uK, %uK)\n",
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guc_wopcm_base / SZ_1K, guc_wopcm_size / SZ_1K);
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check:
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if (__check_layout(i915, wopcm_size, guc_wopcm_base, guc_wopcm_size,
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guc_fw_size, huc_fw_size)) {
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wopcm->guc.base = guc_wopcm_base;
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wopcm->guc.size = guc_wopcm_size;
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GEM_BUG_ON(!wopcm->guc.base);
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GEM_BUG_ON(!wopcm->guc.size);
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}
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}
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