linux/include/soc
Vladimir Oltean a4e044dc4c net: dsa: felix: tag_8021q preparation for multiple CPU ports
Update the VCAP filters to support multiple tag_8021q CPU ports.

TX works using a filter for VLAN ID on the ingress of the CPU port, with
a redirect and a VLAN pop action. This can be updated trivially by
amending the ingress port mask of this rule to match on all tag_8021q
CPU ports.

RX works using a filter for ingress port on the egress of the CPU port,
with a VLAN push action. Here we need to replicate these filters for
each tag_8021q CPU port, and let them all have the same action.
This means that the OCELOT_VCAP_ES0_TAG_8021Q_RXVLAN() cookie needs to
encode a unique value for every {user port, CPU port} pair it's given.
Do this by encoding the CPU port in the upper 16 bits of the cookie, and
the user port in the lower 16 bits.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2022-05-23 10:39:55 +01:00
..
arc clocksource/drivers/arc_timer: Eliminate redefined macro error 2021-10-16 22:15:01 +02:00
at91 ARM: at91: PM: add cpu idle support for sama7g5 2022-02-25 12:36:25 +01:00
bcm2835 firmware: raspberrypi: Add RPI_FIRMWARE_NOTIFY_DISPLAY_DONE 2022-01-11 13:16:10 +01:00
canaan clk: Add RISC-V Canaan Kendryte K210 clock driver 2021-02-22 17:51:04 -08:00
fsl soc: fsl: Replace kernel.h with the necessary inclusions 2022-02-18 17:11:17 -06:00
imx ARM: imx: Initialize SoC ID on i.MX50 2021-05-13 15:42:21 +08:00
mediatek media: memory: mtk-smi: Get rid of mtk_smi_larb_get/put 2022-01-28 15:30:21 +01:00
microchip soc: add microchip polarfire soc system controller 2022-02-25 12:50:59 +01:00
mscc net: dsa: felix: tag_8021q preparation for multiple CPU ports 2022-05-23 10:39:55 +01:00
qcom soc: qcom: spm: Implement support for SAWv4.1, SDM630/660 L2 AVS 2021-09-21 17:41:48 -05:00
rockchip treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288 2019-06-05 17:36:37 +02:00
sa1100 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 2019-06-19 17:09:55 +02:00
sifive riscv: move sifive_l2_cache.h to include/soc 2020-01-12 10:12:44 -08:00
tegra soc/tegra: bpmp: cleanup double word in comment 2022-02-25 14:10:09 +01:00