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7c3df1320e
The code is changed to support the new dynamic logging infrastructure. Following are the levels added. Default is 0 - no logging. 0x40000000 - Module Init & Probe. 0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery. 0x08000000 - IO tracing. 0x04000000 - DPC Thread. 0x02000000 - Async events. 0x01000000 - Timer routines. 0x00800000 - User space. 0x00400000 - Task Management. 0x00200000 - AER/EEH. 0x00100000 - Multi Q. 0x00080000 - P3P Specific. 0x00040000 - Virtual Port. 0x00020000 - Buffer Dump. 0x00010000 - Misc. 0x7fffffff - For enabling all logs, can be too many logs. Setting ql2xextended_error_logging module parameter to any of the above value, will enable the debug for that particular level. Do LOGICAL OR of the value to enable more than one level. Signed-off-by: Saurav Kashyap <saurav.kashyap@qlogic.com> Signed-off-by: Giridhar Malavali <giridhar.malavali@qlogic.com> Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com> Signed-off-by: Joe Carnuccio <joe.carnuccio@qlogic.com> Signed-off-by: Chad Dupuis <chad.dupuis@qlogic.com> Signed-off-by: Madhuranath Iyengar <Madhu.Iyengar@qlogic.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
105 lines
2.4 KiB
C
105 lines
2.4 KiB
C
/*
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* QLogic Fibre Channel HBA Driver
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* Copyright (c) 2003-2011 QLogic Corporation
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*
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* See LICENSE.qla2xxx for copyright and licensing details.
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*/
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/*
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* qla2x00_debounce_register
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* Debounce register.
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*
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* Input:
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* port = register address.
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*
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* Returns:
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* register value.
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*/
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static __inline__ uint16_t
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qla2x00_debounce_register(volatile uint16_t __iomem *addr)
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{
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volatile uint16_t first;
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volatile uint16_t second;
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do {
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first = RD_REG_WORD(addr);
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barrier();
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cpu_relax();
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second = RD_REG_WORD(addr);
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} while (first != second);
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return (first);
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}
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static inline void
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qla2x00_poll(struct rsp_que *rsp)
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{
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unsigned long flags;
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struct qla_hw_data *ha = rsp->hw;
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local_irq_save(flags);
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if (IS_QLA82XX(ha))
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qla82xx_poll(0, rsp);
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else
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ha->isp_ops->intr_handler(0, rsp);
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local_irq_restore(flags);
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}
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static inline uint8_t *
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host_to_fcp_swap(uint8_t *fcp, uint32_t bsize)
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{
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uint32_t *ifcp = (uint32_t *) fcp;
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uint32_t *ofcp = (uint32_t *) fcp;
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uint32_t iter = bsize >> 2;
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for (; iter ; iter--)
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*ofcp++ = swab32(*ifcp++);
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return fcp;
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}
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static inline int
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qla2x00_is_reserved_id(scsi_qla_host_t *vha, uint16_t loop_id)
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{
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struct qla_hw_data *ha = vha->hw;
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if (IS_FWI2_CAPABLE(ha))
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return (loop_id > NPH_LAST_HANDLE);
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return ((loop_id > ha->max_loop_id && loop_id < SNS_FIRST_LOOP_ID) ||
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loop_id == MANAGEMENT_SERVER || loop_id == BROADCAST);
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}
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static inline void
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qla2x00_clean_dsd_pool(struct qla_hw_data *ha, srb_t *sp)
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{
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struct dsd_dma *dsd_ptr, *tdsd_ptr;
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/* clean up allocated prev pool */
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list_for_each_entry_safe(dsd_ptr, tdsd_ptr,
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&((struct crc_context *)sp->ctx)->dsd_list, list) {
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dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr,
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dsd_ptr->dsd_list_dma);
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list_del(&dsd_ptr->list);
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kfree(dsd_ptr);
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}
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INIT_LIST_HEAD(&((struct crc_context *)sp->ctx)->dsd_list);
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}
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static inline void
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qla2x00_set_fcport_state(fc_port_t *fcport, int state)
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{
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int old_state;
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old_state = atomic_read(&fcport->state);
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atomic_set(&fcport->state, state);
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/* Don't print state transitions during initial allocation of fcport */
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if (old_state && old_state != state) {
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ql_dbg(ql_dbg_disc, fcport->vha, 0x207d,
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"FCPort state transitioned from %s to %s - "
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"portid=%02x%02x%02x.\n",
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port_state_str[old_state], port_state_str[state],
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fcport->d_id.b.domain, fcport->d_id.b.area,
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fcport->d_id.b.al_pa);
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}
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}
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