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The integrated assembler of Clang 10 and earlier do not allow to access
the VFP registers through the coprocessor load/store instructions:
arch/arm/vfp/vfpmodule.c:342:2: error: invalid operand for instruction
fmxr(FPEXC, fpexc & ~(FPEXC_EX|FPEXC_DEX|FPEXC_FP2V|FPEXC_VV|FPEXC_TRAP_MASK));
^
arch/arm/vfp/vfpinstr.h:79:6: note: expanded from macro 'fmxr'
asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0"
^
<inline asm>:1:6: note: instantiated into assembly here
mcr p10, 7, r0, cr8, cr0, 0 @ fmxr FPEXC, r0
^
This has been addressed with Clang 11 [0]. However, to support earlier
versions of Clang and for better readability use of VFP assembler
mnemonics still is preferred.
Ideally we would replace this code with the unified assembler language
mnemonics vmrs/vmsr on call sites along with .fpu assembler directives.
The GNU assembler supports the .fpu directive at least since 2.17 (when
documentation has been added). Since Linux requires binutils 2.21 it is
safe to use .fpu directive. However, binutils does not allow to use
FPINST or FPINST2 as an argument to vmrs/vmsr instructions up to
binutils 2.24 (see binutils commit 16d02dc907c5):
arch/arm/vfp/vfphw.S: Assembler messages:
arch/arm/vfp/vfphw.S:162: Error: operand 0 must be FPSID or FPSCR pr FPEXC -- `vmsr FPINST,r6'
arch/arm/vfp/vfphw.S:165: Error: operand 0 must be FPSID or FPSCR pr FPEXC -- `vmsr FPINST2,r8'
arch/arm/vfp/vfphw.S:235: Error: operand 1 must be a VFP extension System Register -- `vmrs r3,FPINST'
arch/arm/vfp/vfphw.S:238: Error: operand 1 must be a VFP extension System Register -- `vmrs r12,FPINST2'
Use as-instr in Kconfig to check if FPINST/FPINST2 can be used. If they
can be used make use of .fpu directives and UAL VFP mnemonics for
register access.
This allows to build vfpmodule.c with Clang and its integrated assembler.
[0] https://reviews.llvm.org/D59733
Link: https://github.com/ClangBuiltLinux/linux/issues/905
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
80 lines
2.0 KiB
C
80 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* arch/arm/include/asm/vfpmacros.h
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*
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* Assembler-only file containing VFP macros and register definitions.
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*/
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#include <asm/hwcap.h>
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#include <asm/vfp.h>
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#ifdef CONFIG_AS_VFP_VMRS_FPINST
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.macro VFPFMRX, rd, sysreg, cond
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vmrs\cond \rd, \sysreg
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.endm
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.macro VFPFMXR, sysreg, rd, cond
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vmsr\cond \sysreg, \rd
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.endm
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#else
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@ Macros to allow building with old toolkits (with no VFP support)
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.macro VFPFMRX, rd, sysreg, cond
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MRC\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMRX \rd, \sysreg
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.endm
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.macro VFPFMXR, sysreg, rd, cond
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MCR\cond p10, 7, \rd, \sysreg, cr0, 0 @ FMXR \sysreg, \rd
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.endm
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#endif
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@ read all the working registers back into the VFP
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.macro VFPFLDMIA, base, tmp
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.fpu vfpv2
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#if __LINUX_ARM_ARCH__ < 6
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fldmiax \base!, {d0-d15}
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#else
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vldmia \base!, {d0-d15}
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#endif
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#ifdef CONFIG_VFPv3
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.fpu vfpv3
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#if __LINUX_ARM_ARCH__ <= 6
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ldr \tmp, =elf_hwcap @ may not have MVFR regs
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ldr \tmp, [\tmp, #0]
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tst \tmp, #HWCAP_VFPD32
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vldmiane \base!, {d16-d31}
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addeq \base, \base, #32*4 @ step over unused register space
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#else
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VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
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and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
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cmp \tmp, #2 @ 32 x 64bit registers?
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vldmiaeq \base!, {d16-d31}
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addne \base, \base, #32*4 @ step over unused register space
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#endif
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#endif
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.endm
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@ write all the working registers out of the VFP
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.macro VFPFSTMIA, base, tmp
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#if __LINUX_ARM_ARCH__ < 6
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fstmiax \base!, {d0-d15}
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#else
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vstmia \base!, {d0-d15}
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#endif
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#ifdef CONFIG_VFPv3
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.fpu vfpv3
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#if __LINUX_ARM_ARCH__ <= 6
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ldr \tmp, =elf_hwcap @ may not have MVFR regs
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ldr \tmp, [\tmp, #0]
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tst \tmp, #HWCAP_VFPD32
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vstmiane \base!, {d16-d31}
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addeq \base, \base, #32*4 @ step over unused register space
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#else
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VFPFMRX \tmp, MVFR0 @ Media and VFP Feature Register 0
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and \tmp, \tmp, #MVFR0_A_SIMD_MASK @ A_SIMD field
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cmp \tmp, #2 @ 32 x 64bit registers?
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vstmiaeq \base!, {d16-d31}
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addne \base, \base, #32*4 @ step over unused register space
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#endif
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#endif
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.endm
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