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When we remove a page table entry, we are very careful to only free the page after we have flushed the TLB, because other CPUs could still be using the page through stale TLB entries until after the flush. However, we have removed the rmap entry for that page early, which means that functions like folio_mkclean() would end up not serializing with the page table lock because the page had already been made invisible to rmap. And that is a problem, because while the TLB entry exists, we could end up with the following situation: (a) one CPU could come in and clean it, never seeing our mapping of the page (b) another CPU could continue to use the stale and dirty TLB entry and continue to write to said page resulting in a page that has been dirtied, but then marked clean again, all while another CPU might have dirtied it some more. End result: possibly lost dirty data. This extends our current TLB gather infrastructure to optionally track a "should I do a delayed page_remove_rmap() for this page after flushing the TLB". It uses the newly introduced 'encoded page pointer' to do that without having to keep separate data around. Note, this is complicated by a couple of issues: - we want to delay the rmap removal, but not past the page table lock, because that simplifies the memcg accounting - only SMP configurations want to delay TLB flushing, since on UP there are obviously no remote TLBs to worry about, and the page table lock means there are no preemption issues either - s390 has its own mmu_gather model that doesn't delay TLB flushing, and as a result also does not want the delayed rmap. As such, we can treat S390 like the UP case and use a common fallback for the "no delays" case. - we can track an enormous number of pages in our mmu_gather structure, with MAX_GATHER_BATCH_COUNT batches of MAX_TABLE_BATCH pages each, all set up to be approximately 10k pending pages. We do not want to have a huge number of batched pages that we then need to check for delayed rmap handling inside the page table lock. Particularly that last point results in a noteworthy detail, where the normal page batch gathering is limited once we have delayed rmaps pending, in such a way that only the last batch (the so-called "active batch") in the mmu_gather structure can have any delayed entries. NOTE! While the "possibly lost dirty data" sounds catastrophic, for this all to happen you need to have a user thread doing either madvise() with MADV_DONTNEED or a full re-mmap() of the area concurrently with another thread continuing to use said mapping. So arguably this is about user space doing crazy things, but from a VM consistency standpoint it's better if we track the dirty bit properly even when user space goes off the rails. [akpm@linux-foundation.org: fix UP build, per Linus] Link: https://lore.kernel.org/all/B88D3073-440A-41C7-95F4-895D3F657EF2@gmail.com/ Link: https://lkml.kernel.org/r/20221109203051.1835763-4-torvalds@linux-foundation.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> Acked-by: Johannes Weiner <hannes@cmpxchg.org> Acked-by: Hugh Dickins <hughd@google.com> Reported-by: Nadav Amit <nadav.amit@gmail.com> Tested-by: Nadav Amit <nadav.amit@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
138 lines
4.2 KiB
C
138 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _S390_TLB_H
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#define _S390_TLB_H
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/*
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* TLB flushing on s390 is complicated. The following requirement
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* from the principles of operation is the most arduous:
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*
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* "A valid table entry must not be changed while it is attached
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* to any CPU and may be used for translation by that CPU except to
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* (1) invalidate the entry by using INVALIDATE PAGE TABLE ENTRY,
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* or INVALIDATE DAT TABLE ENTRY, (2) alter bits 56-63 of a page
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* table entry, or (3) make a change by means of a COMPARE AND SWAP
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* AND PURGE instruction that purges the TLB."
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*
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* The modification of a pte of an active mm struct therefore is
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* a two step process: i) invalidate the pte, ii) store the new pte.
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* This is true for the page protection bit as well.
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* The only possible optimization is to flush at the beginning of
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* a tlb_gather_mmu cycle if the mm_struct is currently not in use.
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*
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* Pages used for the page tables is a different story. FIXME: more
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*/
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void __tlb_remove_table(void *_table);
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static inline void tlb_flush(struct mmu_gather *tlb);
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static inline bool __tlb_remove_page_size(struct mmu_gather *tlb,
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struct encoded_page *page,
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int page_size);
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#define tlb_flush tlb_flush
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#define pte_free_tlb pte_free_tlb
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#define pmd_free_tlb pmd_free_tlb
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#define p4d_free_tlb p4d_free_tlb
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#define pud_free_tlb pud_free_tlb
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#include <asm/tlbflush.h>
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#include <asm-generic/tlb.h>
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/*
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* Release the page cache reference for a pte removed by
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* tlb_ptep_clear_flush. In both flush modes the tlb for a page cache page
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* has already been freed, so just do free_page_and_swap_cache.
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*
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* s390 doesn't delay rmap removal, so there is nothing encoded in
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* the page pointer.
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*/
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static inline bool __tlb_remove_page_size(struct mmu_gather *tlb,
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struct encoded_page *page,
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int page_size)
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{
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free_page_and_swap_cache(encoded_page_ptr(page));
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return false;
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}
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static inline void tlb_flush(struct mmu_gather *tlb)
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{
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__tlb_flush_mm_lazy(tlb->mm);
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}
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/*
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* pte_free_tlb frees a pte table and clears the CRSTE for the
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* page table from the tlb.
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*/
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static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
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unsigned long address)
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{
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__tlb_adjust_range(tlb, address, PAGE_SIZE);
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tlb->mm->context.flush_mm = 1;
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tlb->freed_tables = 1;
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tlb->cleared_pmds = 1;
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/*
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* page_table_free_rcu takes care of the allocation bit masks
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* of the 2K table fragments in the 4K page table page,
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* then calls tlb_remove_table.
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*/
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page_table_free_rcu(tlb, (unsigned long *) pte, address);
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}
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/*
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* pmd_free_tlb frees a pmd table and clears the CRSTE for the
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* segment table entry from the tlb.
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* If the mm uses a two level page table the single pmd is freed
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* as the pgd. pmd_free_tlb checks the asce_limit against 2GB
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* to avoid the double free of the pmd in this case.
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*/
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static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd,
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unsigned long address)
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{
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if (mm_pmd_folded(tlb->mm))
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return;
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pgtable_pmd_page_dtor(virt_to_page(pmd));
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__tlb_adjust_range(tlb, address, PAGE_SIZE);
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tlb->mm->context.flush_mm = 1;
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tlb->freed_tables = 1;
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tlb->cleared_puds = 1;
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tlb_remove_table(tlb, pmd);
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}
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/*
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* p4d_free_tlb frees a pud table and clears the CRSTE for the
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* region second table entry from the tlb.
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* If the mm uses a four level page table the single p4d is freed
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* as the pgd. p4d_free_tlb checks the asce_limit against 8PB
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* to avoid the double free of the p4d in this case.
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*/
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static inline void p4d_free_tlb(struct mmu_gather *tlb, p4d_t *p4d,
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unsigned long address)
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{
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if (mm_p4d_folded(tlb->mm))
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return;
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__tlb_adjust_range(tlb, address, PAGE_SIZE);
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tlb->mm->context.flush_mm = 1;
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tlb->freed_tables = 1;
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tlb_remove_table(tlb, p4d);
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}
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/*
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* pud_free_tlb frees a pud table and clears the CRSTE for the
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* region third table entry from the tlb.
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* If the mm uses a three level page table the single pud is freed
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* as the pgd. pud_free_tlb checks the asce_limit against 4TB
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* to avoid the double free of the pud in this case.
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*/
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static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud,
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unsigned long address)
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{
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if (mm_pud_folded(tlb->mm))
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return;
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tlb->mm->context.flush_mm = 1;
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tlb->freed_tables = 1;
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tlb->cleared_p4ds = 1;
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tlb_remove_table(tlb, pud);
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}
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#endif /* _S390_TLB_H */
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