mirror of
https://github.com/torvalds/linux.git
synced 2024-12-24 11:51:27 +00:00
53b74ed2d0
This reverts commit5ddc7bd43c("mtd: atmel_nand: Support variable RB_EDGE interrupts") Because for current SoCs, the RB_EDGE3(i.e. bit 27) of HSMC_SR register does not exist, the RB_EDGE0 (i.e. bit 24) is the ready/busy line edge status bit. It is a datasheet bug. Cc: <stable@vger.kernel.org> Fixes: commit5ddc7bd43c("mtd: atmel_nand: Support variable RB_EDGE interrupts") Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
117 lines
3.8 KiB
Plaintext
117 lines
3.8 KiB
Plaintext
Atmel NAND flash
|
|
|
|
Required properties:
|
|
- compatible: The possible values are:
|
|
"atmel,at91rm9200-nand"
|
|
"atmel,sama5d2-nand"
|
|
"atmel,sama5d4-nand"
|
|
- reg : should specify localbus address and size used for the chip,
|
|
and hardware ECC controller if available.
|
|
If the hardware ECC is PMECC, it should contain address and size for
|
|
PMECC and PMECC Error Location controller.
|
|
The PMECC lookup table address and size in ROM is optional. If not
|
|
specified, driver will build it in runtime.
|
|
- atmel,nand-addr-offset : offset for the address latch.
|
|
- atmel,nand-cmd-offset : offset for the command latch.
|
|
- #address-cells, #size-cells : Must be present if the device has sub-nodes
|
|
representing partitions.
|
|
|
|
- gpios : specifies the gpio pins to control the NAND device. detect is an
|
|
optional gpio and may be set to 0 if not present.
|
|
|
|
Optional properties:
|
|
- atmel,nand-has-dma : boolean to support dma transfer for nand read/write.
|
|
- nand-ecc-mode : String, operation mode of the NAND ecc mode, soft by default.
|
|
Supported values are: "none", "soft", "hw", "hw_syndrome", "hw_oob_first",
|
|
"soft_bch".
|
|
- atmel,has-pmecc : boolean to enable Programmable Multibit ECC hardware,
|
|
capable of BCH encoding and decoding, on devices where it is present.
|
|
- atmel,pmecc-cap : error correct capability for Programmable Multibit ECC
|
|
Controller. Supported values are: 2, 4, 8, 12, 24. If the compatible string
|
|
is "atmel,sama5d2-nand", 32 is also valid.
|
|
- atmel,pmecc-sector-size : sector size for ECC computation. Supported values
|
|
are: 512, 1024.
|
|
- atmel,pmecc-lookup-table-offset : includes two offsets of lookup table in ROM
|
|
for different sector size. First one is for sector size 512, the next is for
|
|
sector size 1024. If not specified, driver will build the table in runtime.
|
|
- nand-bus-width : 8 or 16 bus width if not present 8
|
|
- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
|
|
|
|
Nand Flash Controller(NFC) is an optional sub-node
|
|
Required properties:
|
|
- compatible : "atmel,sama5d3-nfc".
|
|
- reg : should specify the address and size used for NFC command registers,
|
|
NFC registers and NFC SRAM. NFC SRAM address and size can be absent
|
|
if don't want to use it.
|
|
- clocks: phandle to the peripheral clock
|
|
Optional properties:
|
|
- atmel,write-by-sram: boolean to enable NFC write by SRAM.
|
|
|
|
Examples:
|
|
nand0: nand@40000000,0 {
|
|
compatible = "atmel,at91rm9200-nand";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x40000000 0x10000000
|
|
0xffffe800 0x200
|
|
>;
|
|
atmel,nand-addr-offset = <21>; /* ale */
|
|
atmel,nand-cmd-offset = <22>; /* cle */
|
|
nand-on-flash-bbt;
|
|
nand-ecc-mode = "soft";
|
|
gpios = <&pioC 13 0 /* rdy */
|
|
&pioC 14 0 /* nce */
|
|
0 /* cd */
|
|
>;
|
|
partition@0 {
|
|
...
|
|
};
|
|
};
|
|
|
|
/* for PMECC supported chips */
|
|
nand0: nand@40000000 {
|
|
compatible = "atmel,at91rm9200-nand";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = < 0x40000000 0x10000000 /* bus addr & size */
|
|
0xffffe000 0x00000600 /* PMECC addr & size */
|
|
0xffffe600 0x00000200 /* PMECC ERRLOC addr & size */
|
|
0x00100000 0x00100000 /* ROM addr & size */
|
|
>;
|
|
atmel,nand-addr-offset = <21>; /* ale */
|
|
atmel,nand-cmd-offset = <22>; /* cle */
|
|
nand-on-flash-bbt;
|
|
nand-ecc-mode = "hw";
|
|
atmel,has-pmecc; /* enable PMECC */
|
|
atmel,pmecc-cap = <2>;
|
|
atmel,pmecc-sector-size = <512>;
|
|
atmel,pmecc-lookup-table-offset = <0x8000 0x10000>;
|
|
gpios = <&pioD 5 0 /* rdy */
|
|
&pioD 4 0 /* nce */
|
|
0 /* cd */
|
|
>;
|
|
partition@0 {
|
|
...
|
|
};
|
|
};
|
|
|
|
/* for NFC supported chips */
|
|
nand0: nand@40000000 {
|
|
compatible = "atmel,at91rm9200-nand";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
...
|
|
nfc@70000000 {
|
|
compatible = "atmel,sama5d3-nfc";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clocks = <&hsmc_clk>
|
|
reg = <
|
|
0x70000000 0x10000000 /* NFC Command Registers */
|
|
0xffffc000 0x00000070 /* NFC HSMC regs */
|
|
0x00200000 0x00100000 /* NFC SRAM banks */
|
|
>;
|
|
};
|
|
};
|