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bd0b9ac405
Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
140 lines
4.5 KiB
C
140 lines
4.5 KiB
C
/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Authors: Shlomi Gridish <gridish@freescale.com>
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* Li Yang <leoli@freescale.com>
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*
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* Description:
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* QE IC external definitions and structure.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef _ASM_POWERPC_QE_IC_H
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#define _ASM_POWERPC_QE_IC_H
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#include <linux/irq.h>
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struct device_node;
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struct qe_ic;
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#define NUM_OF_QE_IC_GROUPS 6
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/* Flags when we init the QE IC */
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#define QE_IC_SPREADMODE_GRP_W 0x00000001
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#define QE_IC_SPREADMODE_GRP_X 0x00000002
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#define QE_IC_SPREADMODE_GRP_Y 0x00000004
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#define QE_IC_SPREADMODE_GRP_Z 0x00000008
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#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
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#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
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#define QE_IC_LOW_SIGNAL 0x00000100
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#define QE_IC_HIGH_SIGNAL 0x00000200
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#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
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#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
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#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
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#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
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#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
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#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
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#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
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#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
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#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
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#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
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#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
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#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
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#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
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/* QE interrupt sources groups */
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enum qe_ic_grp_id {
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QE_IC_GRP_W = 0, /* QE interrupt controller group W */
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QE_IC_GRP_X, /* QE interrupt controller group X */
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QE_IC_GRP_Y, /* QE interrupt controller group Y */
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QE_IC_GRP_Z, /* QE interrupt controller group Z */
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QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
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QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
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};
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#ifdef CONFIG_QUICC_ENGINE
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void qe_ic_init(struct device_node *node, unsigned int flags,
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void (*low_handler)(struct irq_desc *desc),
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void (*high_handler)(struct irq_desc *desc));
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unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
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unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
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#else
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static inline void qe_ic_init(struct device_node *node, unsigned int flags,
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void (*low_handler)(struct irq_desc *desc),
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void (*high_handler)(struct irq_desc *desc))
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{}
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static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
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{ return 0; }
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static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
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{ return 0; }
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#endif /* CONFIG_QUICC_ENGINE */
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void qe_ic_set_highest_priority(unsigned int virq, int high);
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int qe_ic_set_priority(unsigned int virq, unsigned int priority);
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int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
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static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
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if (cascade_irq != NO_IRQ)
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generic_handle_irq(cascade_irq);
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}
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static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
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if (cascade_irq != NO_IRQ)
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generic_handle_irq(cascade_irq);
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}
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static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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if (cascade_irq != NO_IRQ)
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generic_handle_irq(cascade_irq);
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chip->irq_eoi(&desc->irq_data);
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}
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static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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if (cascade_irq != NO_IRQ)
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generic_handle_irq(cascade_irq);
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chip->irq_eoi(&desc->irq_data);
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}
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static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
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{
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struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
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unsigned int cascade_irq;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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cascade_irq = qe_ic_get_high_irq(qe_ic);
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if (cascade_irq == NO_IRQ)
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cascade_irq = qe_ic_get_low_irq(qe_ic);
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if (cascade_irq != NO_IRQ)
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generic_handle_irq(cascade_irq);
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chip->irq_eoi(&desc->irq_data);
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}
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#endif /* _ASM_POWERPC_QE_IC_H */
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