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The macrology in cmpxchg.h was designed to allow arbitrary pointer
and integer values to be passed through the routines. To support
cmpxchg() on 64-bit values on the 32-bit tilepro architecture, we
used the idiom "(typeof(val))(typeof(val-val))". This way, in the
"size 8" branch of the switch, when the underlying cmpxchg routine
returns a 64-bit quantity, we cast it first to a typeof(val-val)
quantity (i.e. size_t if "val" is a pointer) with no warnings about
casting between pointers and integers of different sizes, then cast
onwards to typeof(val), again with no warnings. If val is not a
pointer type, the additional cast is a no-op. We can't replace the
typeof(val-val) cast with (for example) unsigned long, since then if
"val" is really a 64-bit type, we cast away the high bits.
HOWEVER, this fails with current gcc (through 4.7 at least) if "val"
is a pointer to an incomplete type. Unfortunately gcc isn't smart
enough to realize that "val - val" will always be a size_t type
even if it's an incomplete type pointer.
Accordingly, I've reworked the way we handle the casting. We have
given up the ability to use cmpxchg() on 64-bit values on tilepro,
which is OK in the kernel since we should use cmpxchg64() explicitly
on such values anyway. As a result, I can just use simple "unsigned
long" casts internally.
As I reworked it, I realized it would be cleaner to move the
architecture-specific conditionals for cmpxchg and xchg out of the
atomic.h headers and into cmpxchg, and then use the cmpxchg() and
xchg() primitives directly in atomic.h and elsewhere. This allowed
the cmpxchg.h header to stand on its own without relying on the
implicit include of it that is performed by <asm/atomic.h>.
It also allowed collapsing the atomic_xchg/atomic_cmpxchg routines
from atomic_{32,64}.h into atomic.h.
I improved the tests that guard the allowed size of the arguments
to the routines to use a __compiletime_error() test. (By avoiding
the use of BUILD_BUG, I could include cmpxchg.h into bitops.h as
well and use the macros there, which is otherwise impossible due
to include order dependency issues.)
The tilepro _atomic_xxx internal methods were previously set up to
take atomic_t and atomic64_t arguments, which isn't as convenient
with the new model, so I modified them to take int or u64 arguments,
which is consistent with how they used the arguments internally
anyway, so provided some nice simplification there too.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
120 lines
3.4 KiB
C
120 lines
3.4 KiB
C
/*
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* Copyright 2011 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*
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* Do not include directly; use <linux/atomic.h>.
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*/
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#ifndef _ASM_TILE_ATOMIC_64_H
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#define _ASM_TILE_ATOMIC_64_H
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#ifndef __ASSEMBLY__
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#include <asm/barrier.h>
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#include <arch/spr_def.h>
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/* First, the 32-bit atomic ops that are "real" on our 64-bit platform. */
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#define atomic_set(v, i) ((v)->counter = (i))
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/*
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* The smp_mb() operations throughout are to support the fact that
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* Linux requires memory barriers before and after the operation,
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* on any routine which updates memory and returns a value.
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*/
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static inline void atomic_add(int i, atomic_t *v)
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{
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__insn_fetchadd4((void *)&v->counter, i);
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}
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static inline int atomic_add_return(int i, atomic_t *v)
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{
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int val;
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smp_mb(); /* barrier for proper semantics */
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val = __insn_fetchadd4((void *)&v->counter, i) + i;
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barrier(); /* the "+ i" above will wait on memory */
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return val;
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}
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static inline int __atomic_add_unless(atomic_t *v, int a, int u)
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{
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int guess, oldval = v->counter;
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do {
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if (oldval == u)
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break;
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guess = oldval;
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oldval = cmpxchg(&v->counter, guess, guess + a);
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} while (guess != oldval);
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return oldval;
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}
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/* Now the true 64-bit operations. */
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#define ATOMIC64_INIT(i) { (i) }
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#define atomic64_read(v) ((v)->counter)
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#define atomic64_set(v, i) ((v)->counter = (i))
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static inline void atomic64_add(long i, atomic64_t *v)
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{
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__insn_fetchadd((void *)&v->counter, i);
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}
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static inline long atomic64_add_return(long i, atomic64_t *v)
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{
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int val;
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smp_mb(); /* barrier for proper semantics */
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val = __insn_fetchadd((void *)&v->counter, i) + i;
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barrier(); /* the "+ i" above will wait on memory */
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return val;
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}
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static inline long atomic64_add_unless(atomic64_t *v, long a, long u)
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{
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long guess, oldval = v->counter;
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do {
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if (oldval == u)
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break;
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guess = oldval;
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oldval = cmpxchg(&v->counter, guess, guess + a);
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} while (guess != oldval);
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return oldval != u;
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}
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#define atomic64_sub_return(i, v) atomic64_add_return(-(i), (v))
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#define atomic64_sub(i, v) atomic64_add(-(i), (v))
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#define atomic64_inc_return(v) atomic64_add_return(1, (v))
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#define atomic64_dec_return(v) atomic64_sub_return(1, (v))
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#define atomic64_inc(v) atomic64_add(1, (v))
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#define atomic64_dec(v) atomic64_sub(1, (v))
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#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
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#define atomic64_dec_and_test(v) (atomic64_dec_return(v) == 0)
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#define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0)
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#define atomic64_add_negative(i, v) (atomic64_add_return((i), (v)) < 0)
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#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
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/* Atomic dec and inc don't implement barrier, so provide them if needed. */
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#define smp_mb__before_atomic_dec() smp_mb()
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#define smp_mb__after_atomic_dec() smp_mb()
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#define smp_mb__before_atomic_inc() smp_mb()
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#define smp_mb__after_atomic_inc() smp_mb()
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/* Define this to indicate that cmpxchg is an efficient operation. */
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#define __HAVE_ARCH_CMPXCHG
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_TILE_ATOMIC_64_H */
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