mirror of
https://github.com/torvalds/linux.git
synced 2024-12-18 09:02:17 +00:00
4a93f21d87
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
42 lines
1.3 KiB
Plaintext
42 lines
1.3 KiB
Plaintext
* Renesas VMSA-Compatible IOMMU
|
|
|
|
The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
|
|
It provides address translation for bus masters outside of the CPU, each
|
|
connected to the IPMMU through a port called micro-TLB.
|
|
|
|
|
|
Required Properties:
|
|
|
|
- compatible: Must contain "renesas,ipmmu-vmsa".
|
|
- reg: Base address and size of the IPMMU registers.
|
|
- interrupts: Specifiers for the MMU fault interrupts. For instances that
|
|
support secure mode two interrupts must be specified, for non-secure and
|
|
secure mode, in that order. For instances that don't support secure mode a
|
|
single interrupt must be specified.
|
|
|
|
- #iommu-cells: Must be 1.
|
|
|
|
Each bus master connected to an IPMMU must reference the IPMMU in its device
|
|
node with the following property:
|
|
|
|
- iommus: A reference to the IPMMU in two cells. The first cell is a phandle
|
|
to the IPMMU and the second cell the number of the micro-TLB that the
|
|
device is connected to.
|
|
|
|
|
|
Example: R8A7791 IPMMU-MX and VSP1-D0 bus master
|
|
|
|
ipmmu_mx: mmu@fe951000 {
|
|
compatible = "renasas,ipmmu-vmsa";
|
|
reg = <0 0xfe951000 0 0x1000>;
|
|
interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 221 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
vsp1@fe928000 {
|
|
...
|
|
iommus = <&ipmmu_mx 13>;
|
|
...
|
|
};
|