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2dc10ad81f
- "genirq: Introduce generic irq migration for cpu hotunplugged" patch merged from tip/irq/for-arm to allow the arm64-specific part to be upstreamed via the arm64 tree - CPU feature detection reworked to cope with heterogeneous systems where CPUs may not have exactly the same features. The features reported by the kernel via internal data structures or ELF_HWCAP are delayed until all the CPUs are up (and before user space starts) - Support for 16KB pages, with the additional bonus of a 36-bit VA space, though the latter only depending on EXPERT - Implement native {relaxed, acquire, release} atomics for arm64 - New ASID allocation algorithm which avoids IPI on roll-over, together with TLB invalidation optimisations (using local vs global where feasible) - KASan support for arm64 - EFI_STUB clean-up and isolation for the kernel proper (required by KASan) - copy_{to,from,in}_user optimisations (sharing the memcpy template) - perf: moving arm64 to the arm32/64 shared PMU framework - L1_CACHE_BYTES increased to 128 to accommodate Cavium hardware - Support for the contiguous PTE hint on kernel mapping (16 consecutive entries may be able to use a single TLB entry) - Generic CONFIG_HZ now used on arm64 - defconfig updates -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWOkmIAAoJEGvWsS0AyF7x4GgQAINU3NePjFFvWZNCkqobeH9+ jFKwtXamIudhTSdnXNXyYWmtRL9Krg3qI4zDQf68dvDFAZAze2kVuOi1yPpCbpFZ /j/afNyQc7+PoyqRAzmT+EMPZlcuOA84Prrl1r3QWZ58QaFeVk/6ZxrHunTHxN0x mR9PIXfWx73MTo+UnG8FChkmEY6LmV4XpemgTaMR9FqFhdT51OZSxDDAYXOTm4JW a5HdN9OWjjJ2rhLlFEaC7tszG9B5doHdy2tr5ge/YERVJzIPDogHkMe8ZhfAJc+x SQU5tKN6Pg4MOi+dLhxlk0/mKCvHLiEQ5KVREJnt8GxupAR54Bat+DQ+rP9cSnpq dRQTcARIOyy9LGgy+ROAsSo+NiyM5WuJ0/WJUYKmgWTJOfczRYoZv6TMKlwNOUYb tGLCZHhKPM3yBHJlWbQykl3xmSuudxCMmjlZzg7B+MVfTP6uo0CRSPmYl+v67q+J bBw/Z2RYXWYGnvlc6OfbMeImI6prXeE36+5ytyJFga0m+IqcTzRGzjcLxKEvdbiU pr8n9i+hV9iSsT/UwukXZ8ay6zH7PrTLzILWQlieutfXlvha7MYeGxnkbLmdYcfe GCj374io5cdImHcVKmfhnOMlFOLuOHphl9cmsd/O2LmCIqBj9BIeNH2Om8mHVK2F YHczMdpESlJApE7kUc1e =3six -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Catalin Marinas: - "genirq: Introduce generic irq migration for cpu hotunplugged" patch merged from tip/irq/for-arm to allow the arm64-specific part to be upstreamed via the arm64 tree - CPU feature detection reworked to cope with heterogeneous systems where CPUs may not have exactly the same features. The features reported by the kernel via internal data structures or ELF_HWCAP are delayed until all the CPUs are up (and before user space starts) - Support for 16KB pages, with the additional bonus of a 36-bit VA space, though the latter only depending on EXPERT - Implement native {relaxed, acquire, release} atomics for arm64 - New ASID allocation algorithm which avoids IPI on roll-over, together with TLB invalidation optimisations (using local vs global where feasible) - KASan support for arm64 - EFI_STUB clean-up and isolation for the kernel proper (required by KASan) - copy_{to,from,in}_user optimisations (sharing the memcpy template) - perf: moving arm64 to the arm32/64 shared PMU framework - L1_CACHE_BYTES increased to 128 to accommodate Cavium hardware - Support for the contiguous PTE hint on kernel mapping (16 consecutive entries may be able to use a single TLB entry) - Generic CONFIG_HZ now used on arm64 - defconfig updates * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (91 commits) arm64/efi: fix libstub build under CONFIG_MODVERSIONS ARM64: Enable multi-core scheduler support by default arm64/efi: move arm64 specific stub C code to libstub arm64: page-align sections for DEBUG_RODATA arm64: Fix build with CONFIG_ZONE_DMA=n arm64: Fix compat register mappings arm64: Increase the max granular size arm64: remove bogus TASK_SIZE_64 check arm64: make Timer Interrupt Frequency selectable arm64/mm: use PAGE_ALIGNED instead of IS_ALIGNED arm64: cachetype: fix definitions of ICACHEF_* flags arm64: cpufeature: declare enable_cpu_capabilities as static genirq: Make the cpuhotplug migration code less noisy arm64: Constify hwcap name string arrays arm64/kvm: Make use of the system wide safe values arm64/debug: Make use of the system wide safe value arm64: Move FP/ASIMD hwcap handling to common code arm64/HWCAP: Use system wide safe values arm64/capabilities: Make use of system wide safe value arm64: Delay cpu feature capability checks ...
171 lines
4.3 KiB
C
171 lines
4.3 KiB
C
/*
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* Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_CPUFEATURE_H
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#define __ASM_CPUFEATURE_H
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#include <asm/hwcap.h>
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#include <asm/sysreg.h>
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/*
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* In the arm64 world (as in the ARM world), elf_hwcap is used both internally
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* in the kernel and for user space to keep track of which optional features
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* are supported by the current system. So let's map feature 'x' to HWCAP_x.
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* Note that HWCAP_x constants are bit fields so we need to take the log.
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*/
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#define MAX_CPU_FEATURES (8 * sizeof(elf_hwcap))
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#define cpu_feature(x) ilog2(HWCAP_ ## x)
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#define ARM64_WORKAROUND_CLEAN_CACHE 0
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#define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1
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#define ARM64_WORKAROUND_845719 2
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#define ARM64_HAS_SYSREG_GIC_CPUIF 3
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#define ARM64_HAS_PAN 4
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#define ARM64_HAS_LSE_ATOMICS 5
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#define ARM64_WORKAROUND_CAVIUM_23154 6
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#define ARM64_NCAPS 7
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#ifndef __ASSEMBLY__
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#include <linux/kernel.h>
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/* CPU feature register tracking */
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enum ftr_type {
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FTR_EXACT, /* Use a predefined safe value */
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FTR_LOWER_SAFE, /* Smaller value is safe */
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FTR_HIGHER_SAFE,/* Bigger value is safe */
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};
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#define FTR_STRICT true /* SANITY check strict matching required */
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#define FTR_NONSTRICT false /* SANITY check ignored */
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struct arm64_ftr_bits {
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bool strict; /* CPU Sanity check: strict matching required ? */
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enum ftr_type type;
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u8 shift;
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u8 width;
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s64 safe_val; /* safe value for discrete features */
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};
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/*
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* @arm64_ftr_reg - Feature register
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* @strict_mask Bits which should match across all CPUs for sanity.
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* @sys_val Safe value across the CPUs (system view)
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*/
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struct arm64_ftr_reg {
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u32 sys_id;
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const char *name;
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u64 strict_mask;
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u64 sys_val;
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struct arm64_ftr_bits *ftr_bits;
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};
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struct arm64_cpu_capabilities {
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const char *desc;
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u16 capability;
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bool (*matches)(const struct arm64_cpu_capabilities *);
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void (*enable)(void *); /* Called on all active CPUs */
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union {
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struct { /* To be used for erratum handling only */
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u32 midr_model;
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u32 midr_range_min, midr_range_max;
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};
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struct { /* Feature register checking */
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u32 sys_reg;
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int field_pos;
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int min_field_value;
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int hwcap_type;
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unsigned long hwcap;
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};
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};
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};
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extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
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static inline bool cpu_have_feature(unsigned int num)
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{
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return elf_hwcap & (1UL << num);
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}
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static inline bool cpus_have_cap(unsigned int num)
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{
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if (num >= ARM64_NCAPS)
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return false;
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return test_bit(num, cpu_hwcaps);
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}
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static inline void cpus_set_cap(unsigned int num)
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{
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if (num >= ARM64_NCAPS)
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pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n",
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num, ARM64_NCAPS);
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else
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__set_bit(num, cpu_hwcaps);
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}
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static inline int __attribute_const__
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cpuid_feature_extract_field_width(u64 features, int field, int width)
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{
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return (s64)(features << (64 - width - field)) >> (64 - width);
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}
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static inline int __attribute_const__
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cpuid_feature_extract_field(u64 features, int field)
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{
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return cpuid_feature_extract_field_width(features, field, 4);
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}
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static inline u64 arm64_ftr_mask(struct arm64_ftr_bits *ftrp)
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{
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return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
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}
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static inline s64 arm64_ftr_value(struct arm64_ftr_bits *ftrp, u64 val)
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{
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return cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width);
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}
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static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
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{
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return cpuid_feature_extract_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||
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cpuid_feature_extract_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;
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}
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void __init setup_cpu_features(void);
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void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
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const char *info);
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void check_local_cpu_errata(void);
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#ifdef CONFIG_HOTPLUG_CPU
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void verify_local_cpu_capabilities(void);
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#else
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static inline void verify_local_cpu_capabilities(void)
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{
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}
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#endif
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u64 read_system_reg(u32 id);
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static inline bool cpu_supports_mixed_endian_el0(void)
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{
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return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
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}
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static inline bool system_supports_mixed_endian_el0(void)
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{
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return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1));
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}
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#endif /* __ASSEMBLY__ */
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#endif
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