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b1b6802586
Between the addition of the ecm/mcm law nodes and the fact that the
get_immrbase() has been using the range property of the SoC to determine
the base address of CCSR space we no longer need the reg property at
the soc node level. It has been ill specified and varied between device
trees to cover either the {e,m}cm-law node, some odd subset of CCSR
space or all of CCSR space.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
351 lines
7.4 KiB
Plaintext
351 lines
7.4 KiB
Plaintext
/*
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* Device Tree Source for the Socrates board (MPC8544).
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*
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* Copyright (c) 2008 Emcraft Systems.
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* Sergei Poselenov, <sposelenov@emcraft.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "abb,socrates";
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compatible = "abb,socrates";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8544@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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next-level-cache = <&L2>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x00000000>; // Filled in by U-Boot
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};
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soc8544@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <0x00000000 0xe0000000 0x00100000>;
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bus-frequency = <0>; // Filled in by U-Boot
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compatible = "fsl,mpc8544-immr", "simple-bus";
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ecm-law@0 {
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compatible = "fsl,ecm-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <10>;
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};
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ecm@1000 {
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compatible = "fsl,mpc8544-ecm", "fsl,ecm";
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reg = <0x1000 0x1000>;
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interrupts = <17 2>;
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interrupt-parent = <&mpic>;
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};
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memory-controller@2000 {
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compatible = "fsl,mpc8544-memory-controller";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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};
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L2: l2-cache-controller@20000 {
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compatible = "fsl,mpc8544-l2-cache-controller";
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reg = <0x20000 0x1000>;
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cache-line-size = <32>;
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cache-size = <0x40000>; // L2, 256K
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interrupt-parent = <&mpic>;
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interrupts = <16 2>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl,mpc8544-i2c", "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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fsl,preserve-clocking;
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dtt@28 {
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compatible = "winbond,w83782d";
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reg = <0x28>;
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};
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rtc@32 {
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compatible = "epson,rx8025";
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reg = <0x32>;
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interrupts = <7 1>;
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interrupt-parent = <&mpic>;
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};
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dtt@4c {
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compatible = "dallas,ds75";
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reg = <0x4c>;
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};
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ts@4a {
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compatible = "ti,tsc2003";
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reg = <0x4a>;
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interrupt-parent = <&mpic>;
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interrupts = <8 1>;
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};
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl,mpc8544-i2c", "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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fsl,preserve-clocking;
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};
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enet0: ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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ranges = <0x0 0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <29 2 30 2 34 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy0>;
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tbi-handle = <&tbi0>;
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phy-connection-type = "rgmii-id";
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x520 0x20>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <0 1>;
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <0 1>;
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reg = <1>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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};
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};
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};
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enet1: ethernet@26000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x26000 0x1000>;
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ranges = <0x0 0x26000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <31 2 32 2 33 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy1>;
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tbi-handle = <&tbi1>;
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phy-connection-type = "rgmii-id";
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x520 0x20>;
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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};
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};
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <42 2>;
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interrupt-parent = <&mpic>;
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};
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global-utilities@e0000 { //global utilities block
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compatible = "fsl,mpc8548-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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mpic: pic@40000 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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};
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localbus {
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compatible = "fsl,mpc8544-localbus",
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"fsl,pq3-localbus",
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"simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <0xe0005000 0x40>;
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ranges = <0 0 0xfc000000 0x04000000
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2 0 0xc8000000 0x04000000
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3 0 0xc0000000 0x00100000
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>; /* Overwritten by U-Boot */
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nor_flash@0,0 {
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compatible = "amd,s29gl256n", "cfi-flash";
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bank-width = <2>;
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reg = <0x0 0x000000 0x4000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "kernel";
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reg = <0x0 0x1e0000>;
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read-only;
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};
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partition@1e0000 {
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label = "dtb";
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reg = <0x1e0000 0x20000>;
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};
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partition@200000 {
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label = "root";
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reg = <0x200000 0x200000>;
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};
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partition@400000 {
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label = "user";
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reg = <0x400000 0x3b80000>;
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};
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partition@3f80000 {
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label = "env";
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reg = <0x3f80000 0x40000>;
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read-only;
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};
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partition@3fc0000 {
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label = "u-boot";
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reg = <0x3fc0000 0x40000>;
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read-only;
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};
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};
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display@2,0 {
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compatible = "fujitsu,lime";
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reg = <2 0x0 0x4000000>;
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interrupt-parent = <&mpic>;
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interrupts = <6 1>;
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};
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fpga_pic: fpga-pic@3,10 {
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compatible = "abb,socrates-fpga-pic";
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reg = <3 0x10 0x10>;
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interrupt-controller;
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/* IRQs 2, 10, 11, active low, level-sensitive */
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interrupts = <2 1 10 1 11 1>;
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interrupt-parent = <&mpic>;
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#interrupt-cells = <3>;
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};
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spi@3,60 {
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compatible = "abb,socrates-spi";
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reg = <3 0x60 0x10>;
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interrupts = <8 4 0>; // number, type, routing
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interrupt-parent = <&fpga_pic>;
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};
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nand@3,70 {
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compatible = "abb,socrates-nand";
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reg = <3 0x70 0x04>;
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bank-width = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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data@0 {
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label = "data";
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reg = <0x0 0x40000000>;
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};
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};
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can@3,100 {
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compatible = "philips,sja1000";
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reg = <3 0x100 0x80>;
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interrupts = <2 8 1>; // number, type, routing
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interrupt-parent = <&fpga_pic>;
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};
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};
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pci0: pci@e0008000 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "fsl,mpc8540-pci";
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device_type = "pci";
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reg = <0xe0008000 0x1000>;
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clock-frequency = <66666666>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x11 */
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0x8800 0x0 0x0 1 &mpic 5 1
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/* IDSEL 0x12 */
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0x9000 0x0 0x0 1 &mpic 4 1>;
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interrupt-parent = <&mpic>;
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interrupts = <24 2>;
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bus-range = <0x0 0x0>;
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
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0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
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};
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};
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