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a7b3474cbb
Sami reported that run_on_irqstack_cond() requires the caller to cast
functions to mismatching types, which trips indirect call Control-Flow
Integrity (CFI) in Clang.
Instead of disabling CFI on that function, provide proper helpers for
the three call variants. The actual ASM code stays the same as that is
out of reach.
[ bp: Fix __run_on_irqstack() prototype to match. ]
Fixes: 931b941459
("x86/entry: Provide helpers for executing on the irqstack")
Reported-by: Nathan Chancellor <natechancellor@gmail.com>
Reported-by: Sami Tolvanen <samitolvanen@google.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Tested-by: Sami Tolvanen <samitolvanen@google.com>
Cc: <stable@vger.kernel.org>
Link: https://github.com/ClangBuiltLinux/linux/issues/1052
Link: https://lkml.kernel.org/r/87pn6eb5tv.fsf@nanos.tec.linutronix.de
377 lines
10 KiB
C
377 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Common interrupt code for 32 and 64 bit
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*/
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#include <linux/cpu.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/of.h>
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#include <linux/seq_file.h>
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#include <linux/smp.h>
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#include <linux/ftrace.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/irq.h>
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#include <asm/irq_stack.h>
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#include <asm/apic.h>
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#include <asm/io_apic.h>
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#include <asm/irq.h>
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#include <asm/mce.h>
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#include <asm/hw_irq.h>
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#include <asm/desc.h>
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#include <asm/traps.h>
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#define CREATE_TRACE_POINTS
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#include <asm/trace/irq_vectors.h>
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DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
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EXPORT_PER_CPU_SYMBOL(irq_stat);
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atomic_t irq_err_count;
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/*
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* 'what should we do if we get a hw irq event on an illegal vector'.
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* each architecture has to answer this themselves.
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*/
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void ack_bad_irq(unsigned int irq)
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{
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if (printk_ratelimit())
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pr_err("unexpected IRQ trap at vector %02x\n", irq);
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/*
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* Currently unexpected vectors happen only on SMP and APIC.
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* We _must_ ack these because every local APIC has only N
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* irq slots per priority level, and a 'hanging, unacked' IRQ
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* holds up an irq slot - in excessive cases (when multiple
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* unexpected vectors occur) that might lock up the APIC
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* completely.
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* But only ack when the APIC is enabled -AK
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*/
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ack_APIC_irq();
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}
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#define irq_stats(x) (&per_cpu(irq_stat, x))
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/*
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* /proc/interrupts printing for arch specific interrupts
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*/
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int arch_show_interrupts(struct seq_file *p, int prec)
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{
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int j;
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seq_printf(p, "%*s: ", prec, "NMI");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
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seq_puts(p, " Non-maskable interrupts\n");
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#ifdef CONFIG_X86_LOCAL_APIC
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seq_printf(p, "%*s: ", prec, "LOC");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
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seq_puts(p, " Local timer interrupts\n");
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seq_printf(p, "%*s: ", prec, "SPU");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
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seq_puts(p, " Spurious interrupts\n");
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seq_printf(p, "%*s: ", prec, "PMI");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
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seq_puts(p, " Performance monitoring interrupts\n");
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seq_printf(p, "%*s: ", prec, "IWI");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
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seq_puts(p, " IRQ work interrupts\n");
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seq_printf(p, "%*s: ", prec, "RTR");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
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seq_puts(p, " APIC ICR read retries\n");
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if (x86_platform_ipi_callback) {
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seq_printf(p, "%*s: ", prec, "PLT");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
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seq_puts(p, " Platform interrupts\n");
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}
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#endif
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#ifdef CONFIG_SMP
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seq_printf(p, "%*s: ", prec, "RES");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
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seq_puts(p, " Rescheduling interrupts\n");
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seq_printf(p, "%*s: ", prec, "CAL");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
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seq_puts(p, " Function call interrupts\n");
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seq_printf(p, "%*s: ", prec, "TLB");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
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seq_puts(p, " TLB shootdowns\n");
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#endif
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#ifdef CONFIG_X86_THERMAL_VECTOR
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seq_printf(p, "%*s: ", prec, "TRM");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
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seq_puts(p, " Thermal event interrupts\n");
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#endif
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#ifdef CONFIG_X86_MCE_THRESHOLD
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seq_printf(p, "%*s: ", prec, "THR");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
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seq_puts(p, " Threshold APIC interrupts\n");
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#endif
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#ifdef CONFIG_X86_MCE_AMD
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seq_printf(p, "%*s: ", prec, "DFR");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count);
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seq_puts(p, " Deferred Error APIC interrupts\n");
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#endif
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#ifdef CONFIG_X86_MCE
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seq_printf(p, "%*s: ", prec, "MCE");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
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seq_puts(p, " Machine check exceptions\n");
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seq_printf(p, "%*s: ", prec, "MCP");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
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seq_puts(p, " Machine check polls\n");
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#endif
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#ifdef CONFIG_X86_HV_CALLBACK_VECTOR
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if (test_bit(HYPERVISOR_CALLBACK_VECTOR, system_vectors)) {
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seq_printf(p, "%*s: ", prec, "HYP");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ",
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irq_stats(j)->irq_hv_callback_count);
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seq_puts(p, " Hypervisor callback interrupts\n");
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}
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#endif
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#if IS_ENABLED(CONFIG_HYPERV)
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if (test_bit(HYPERV_REENLIGHTENMENT_VECTOR, system_vectors)) {
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seq_printf(p, "%*s: ", prec, "HRE");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ",
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irq_stats(j)->irq_hv_reenlightenment_count);
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seq_puts(p, " Hyper-V reenlightenment interrupts\n");
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}
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if (test_bit(HYPERV_STIMER0_VECTOR, system_vectors)) {
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seq_printf(p, "%*s: ", prec, "HVS");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ",
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irq_stats(j)->hyperv_stimer0_count);
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seq_puts(p, " Hyper-V stimer0 interrupts\n");
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}
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#endif
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seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
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#if defined(CONFIG_X86_IO_APIC)
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seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
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#endif
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#ifdef CONFIG_HAVE_KVM
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seq_printf(p, "%*s: ", prec, "PIN");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
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seq_puts(p, " Posted-interrupt notification event\n");
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seq_printf(p, "%*s: ", prec, "NPI");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ",
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irq_stats(j)->kvm_posted_intr_nested_ipis);
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seq_puts(p, " Nested posted-interrupt event\n");
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seq_printf(p, "%*s: ", prec, "PIW");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ",
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irq_stats(j)->kvm_posted_intr_wakeup_ipis);
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seq_puts(p, " Posted-interrupt wakeup event\n");
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#endif
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return 0;
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}
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/*
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* /proc/stat helpers
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*/
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u64 arch_irq_stat_cpu(unsigned int cpu)
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{
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u64 sum = irq_stats(cpu)->__nmi_count;
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#ifdef CONFIG_X86_LOCAL_APIC
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sum += irq_stats(cpu)->apic_timer_irqs;
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sum += irq_stats(cpu)->irq_spurious_count;
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sum += irq_stats(cpu)->apic_perf_irqs;
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sum += irq_stats(cpu)->apic_irq_work_irqs;
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sum += irq_stats(cpu)->icr_read_retry_count;
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if (x86_platform_ipi_callback)
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sum += irq_stats(cpu)->x86_platform_ipis;
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#endif
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#ifdef CONFIG_SMP
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sum += irq_stats(cpu)->irq_resched_count;
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sum += irq_stats(cpu)->irq_call_count;
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#endif
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#ifdef CONFIG_X86_THERMAL_VECTOR
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sum += irq_stats(cpu)->irq_thermal_count;
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#endif
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#ifdef CONFIG_X86_MCE_THRESHOLD
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sum += irq_stats(cpu)->irq_threshold_count;
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#endif
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#ifdef CONFIG_X86_MCE
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sum += per_cpu(mce_exception_count, cpu);
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sum += per_cpu(mce_poll_count, cpu);
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#endif
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return sum;
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}
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u64 arch_irq_stat(void)
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{
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u64 sum = atomic_read(&irq_err_count);
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return sum;
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}
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static __always_inline void handle_irq(struct irq_desc *desc,
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struct pt_regs *regs)
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{
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if (IS_ENABLED(CONFIG_X86_64))
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run_irq_on_irqstack_cond(desc->handle_irq, desc, regs);
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else
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__handle_irq(desc, regs);
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}
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/*
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* common_interrupt() handles all normal device IRQ's (the special SMP
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* cross-CPU interrupts have their own entry points).
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*/
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DEFINE_IDTENTRY_IRQ(common_interrupt)
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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struct irq_desc *desc;
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/* entry code tells RCU that we're not quiescent. Check it. */
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RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
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desc = __this_cpu_read(vector_irq[vector]);
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if (likely(!IS_ERR_OR_NULL(desc))) {
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handle_irq(desc, regs);
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} else {
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ack_APIC_irq();
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if (desc == VECTOR_UNUSED) {
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pr_emerg_ratelimited("%s: %d.%u No irq handler for vector\n",
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__func__, smp_processor_id(),
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vector);
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} else {
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__this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
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}
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}
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set_irq_regs(old_regs);
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}
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#ifdef CONFIG_X86_LOCAL_APIC
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/* Function pointer for generic interrupt vector handling */
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void (*x86_platform_ipi_callback)(void) = NULL;
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/*
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* Handler for X86_PLATFORM_IPI_VECTOR.
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*/
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DEFINE_IDTENTRY_SYSVEC(sysvec_x86_platform_ipi)
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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ack_APIC_irq();
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trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
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inc_irq_stat(x86_platform_ipis);
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if (x86_platform_ipi_callback)
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x86_platform_ipi_callback();
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trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
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set_irq_regs(old_regs);
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}
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#endif
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#ifdef CONFIG_HAVE_KVM
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static void dummy_handler(void) {}
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static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
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void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
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{
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if (handler)
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kvm_posted_intr_wakeup_handler = handler;
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else
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kvm_posted_intr_wakeup_handler = dummy_handler;
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}
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EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
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/*
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* Handler for POSTED_INTERRUPT_VECTOR.
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*/
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DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_ipi)
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{
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ack_APIC_irq();
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inc_irq_stat(kvm_posted_intr_ipis);
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}
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/*
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* Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
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*/
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DEFINE_IDTENTRY_SYSVEC(sysvec_kvm_posted_intr_wakeup_ipi)
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{
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ack_APIC_irq();
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inc_irq_stat(kvm_posted_intr_wakeup_ipis);
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kvm_posted_intr_wakeup_handler();
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}
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/*
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* Handler for POSTED_INTERRUPT_NESTED_VECTOR.
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*/
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DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_nested_ipi)
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{
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ack_APIC_irq();
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inc_irq_stat(kvm_posted_intr_nested_ipis);
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}
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#endif
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#ifdef CONFIG_HOTPLUG_CPU
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/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
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void fixup_irqs(void)
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{
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unsigned int irr, vector;
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struct irq_desc *desc;
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struct irq_data *data;
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struct irq_chip *chip;
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irq_migrate_all_off_this_cpu();
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/*
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* We can remove mdelay() and then send spuriuous interrupts to
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* new cpu targets for all the irqs that were handled previously by
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* this cpu. While it works, I have seen spurious interrupt messages
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* (nothing wrong but still...).
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*
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* So for now, retain mdelay(1) and check the IRR and then send those
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* interrupts to new targets as this cpu is already offlined...
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*/
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mdelay(1);
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/*
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* We can walk the vector array of this cpu without holding
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* vector_lock because the cpu is already marked !online, so
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* nothing else will touch it.
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*/
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for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
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if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector])))
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continue;
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irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
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if (irr & (1 << (vector % 32))) {
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desc = __this_cpu_read(vector_irq[vector]);
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raw_spin_lock(&desc->lock);
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data = irq_desc_get_irq_data(desc);
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chip = irq_data_get_irq_chip(data);
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if (chip->irq_retrigger) {
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chip->irq_retrigger(data);
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__this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
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}
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raw_spin_unlock(&desc->lock);
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}
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if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
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__this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
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}
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}
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#endif
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