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All files in this driver directory contain the following notice:
See LICENSE.qla2xxx for copyright and licensing details.
LICENSE.qla2xxx can be found in Documentation/scsi/. The file contains:
- A copyright notice
This copyright notice is redundant as all files contain the same
copyright notice already
- A license notice
You may modify and redistribute the device driver code under the
GNU General Public License (a copy of which is attached hereto as
Exhibit A) published by the Free Software Foundation (version 2).
This can be replaced with the corresponding SPDX license identifier
(GPL-2.0-only) in the source files which reference this license
file.
- The full GPLv2 license text
A redundant copy of LICENSES/preferred/GPL-2.0
Remove the notices and add the SPDX license identifier GPL-2.0-only to the
source files.
Finally remove the now redundant LICENSE.qla2xxx file.
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Acked-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Acked-by: Nilesh Javali <njavali@marvell.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
246 lines
4.7 KiB
C
246 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* QLogic Fibre Channel HBA Driver
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* Copyright (c) 2003-2014 QLogic Corporation
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*/
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#ifndef __QLA_DMP27_H__
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#define __QLA_DMP27_H__
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#define IOBASE_ADDR offsetof(struct device_reg_24xx, iobase_addr)
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struct __packed qla27xx_fwdt_template {
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__le32 template_type;
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__le32 entry_offset;
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uint32_t template_size;
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uint32_t count; /* borrow field for running/residual count */
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__le32 entry_count;
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uint32_t template_version;
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__le32 capture_timestamp;
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uint32_t template_checksum;
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uint32_t reserved_2;
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__le32 driver_info[3];
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uint32_t saved_state[16];
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uint32_t reserved_3[8];
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__le32 firmware_version[5];
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};
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#define TEMPLATE_TYPE_FWDUMP 99
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#define ENTRY_TYPE_NOP 0
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#define ENTRY_TYPE_TMP_END 255
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#define ENTRY_TYPE_RD_IOB_T1 256
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#define ENTRY_TYPE_WR_IOB_T1 257
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#define ENTRY_TYPE_RD_IOB_T2 258
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#define ENTRY_TYPE_WR_IOB_T2 259
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#define ENTRY_TYPE_RD_PCI 260
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#define ENTRY_TYPE_WR_PCI 261
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#define ENTRY_TYPE_RD_RAM 262
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#define ENTRY_TYPE_GET_QUEUE 263
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#define ENTRY_TYPE_GET_FCE 264
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#define ENTRY_TYPE_PSE_RISC 265
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#define ENTRY_TYPE_RST_RISC 266
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#define ENTRY_TYPE_DIS_INTR 267
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#define ENTRY_TYPE_GET_HBUF 268
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#define ENTRY_TYPE_SCRATCH 269
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#define ENTRY_TYPE_RDREMREG 270
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#define ENTRY_TYPE_WRREMREG 271
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#define ENTRY_TYPE_RDREMRAM 272
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#define ENTRY_TYPE_PCICFG 273
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#define ENTRY_TYPE_GET_SHADOW 274
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#define ENTRY_TYPE_WRITE_BUF 275
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#define ENTRY_TYPE_CONDITIONAL 276
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#define ENTRY_TYPE_RDPEPREG 277
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#define ENTRY_TYPE_WRPEPREG 278
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#define CAPTURE_FLAG_PHYS_ONLY BIT_0
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#define CAPTURE_FLAG_PHYS_VIRT BIT_1
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#define DRIVER_FLAG_SKIP_ENTRY BIT_7
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struct __packed qla27xx_fwdt_entry {
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struct __packed {
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__le32 type;
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__le32 size;
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uint32_t reserved_1;
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uint8_t capture_flags;
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uint8_t reserved_2[2];
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uint8_t driver_flags;
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} hdr;
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union __packed {
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struct __packed {
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} t0;
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struct __packed {
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} t255;
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struct __packed {
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__le32 base_addr;
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uint8_t reg_width;
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__le16 reg_count;
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uint8_t pci_offset;
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} t256;
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struct __packed {
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__le32 base_addr;
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__le32 write_data;
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uint8_t pci_offset;
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uint8_t reserved[3];
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} t257;
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struct __packed {
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__le32 base_addr;
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uint8_t reg_width;
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__le16 reg_count;
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uint8_t pci_offset;
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uint8_t banksel_offset;
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uint8_t reserved[3];
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__le32 bank;
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} t258;
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struct __packed {
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__le32 base_addr;
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__le32 write_data;
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uint8_t reserved[2];
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uint8_t pci_offset;
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uint8_t banksel_offset;
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__le32 bank;
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} t259;
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struct __packed {
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uint8_t pci_offset;
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uint8_t reserved[3];
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} t260;
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struct __packed {
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uint8_t pci_offset;
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uint8_t reserved[3];
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__le32 write_data;
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} t261;
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struct __packed {
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uint8_t ram_area;
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uint8_t reserved[3];
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__le32 start_addr;
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__le32 end_addr;
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} t262;
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struct __packed {
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uint32_t num_queues;
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uint8_t queue_type;
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uint8_t reserved[3];
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} t263;
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struct __packed {
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uint32_t fce_trace_size;
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uint64_t write_pointer;
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uint64_t base_pointer;
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uint32_t fce_enable_mb0;
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uint32_t fce_enable_mb2;
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uint32_t fce_enable_mb3;
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uint32_t fce_enable_mb4;
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uint32_t fce_enable_mb5;
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uint32_t fce_enable_mb6;
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} t264;
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struct __packed {
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} t265;
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struct __packed {
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} t266;
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struct __packed {
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uint8_t pci_offset;
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uint8_t reserved[3];
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__le32 data;
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} t267;
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struct __packed {
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uint8_t buf_type;
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uint8_t reserved[3];
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uint32_t buf_size;
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uint64_t start_addr;
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} t268;
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struct __packed {
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uint32_t scratch_size;
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} t269;
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struct __packed {
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__le32 addr;
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__le32 count;
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} t270;
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struct __packed {
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__le32 addr;
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__le32 data;
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} t271;
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struct __packed {
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__le32 addr;
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__le32 count;
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} t272;
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struct __packed {
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__le32 addr;
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__le32 count;
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} t273;
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struct __packed {
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uint32_t num_queues;
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uint8_t queue_type;
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uint8_t reserved[3];
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} t274;
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struct __packed {
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__le32 length;
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uint8_t buffer[];
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} t275;
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struct __packed {
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__le32 cond1;
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__le32 cond2;
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} t276;
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struct __packed {
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__le32 cmd_addr;
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__le32 wr_cmd_data;
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__le32 data_addr;
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} t277;
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struct __packed {
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__le32 cmd_addr;
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__le32 wr_cmd_data;
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__le32 data_addr;
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__le32 wr_data;
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} t278;
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};
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};
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#define T262_RAM_AREA_CRITICAL_RAM 1
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#define T262_RAM_AREA_EXTERNAL_RAM 2
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#define T262_RAM_AREA_SHARED_RAM 3
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#define T262_RAM_AREA_DDR_RAM 4
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#define T262_RAM_AREA_MISC 5
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#define T263_QUEUE_TYPE_REQ 1
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#define T263_QUEUE_TYPE_RSP 2
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#define T263_QUEUE_TYPE_ATIO 3
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#define T268_BUF_TYPE_EXTD_TRACE 1
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#define T268_BUF_TYPE_EXCH_BUFOFF 2
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#define T268_BUF_TYPE_EXTD_LOGIN 3
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#define T268_BUF_TYPE_REQ_MIRROR 4
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#define T268_BUF_TYPE_RSP_MIRROR 5
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#define T274_QUEUE_TYPE_REQ_SHAD 1
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#define T274_QUEUE_TYPE_RSP_SHAD 2
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#define T274_QUEUE_TYPE_ATIO_SHAD 3
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#endif
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