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8c462d5648
SMCCCv1.3 added a hint bit which callers can set in an SMCCC function ID
(AKA "FID") to indicate that it is acceptable for the SMCCC
implementation to discard SVE and/or SME state over a specific SMCCC
call. The kernel support for using this hint is broken and SMCCC calls
may clobber the SVE and/or SME state of arbitrary tasks, though FPSIMD
state is unaffected.
The kernel support is intended to use the hint when there is no SVE or
SME state to save, and to do this it checks whether TIF_FOREIGN_FPSTATE
is set or TIF_SVE is clear in assembly code:
| ldr <flags>, [<current_task>, #TSK_TI_FLAGS]
| tbnz <flags>, #TIF_FOREIGN_FPSTATE, 1f // Any live FP state?
| tbnz <flags>, #TIF_SVE, 2f // Does that state include SVE?
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| 1: orr <fid>, <fid>, ARM_SMCCC_1_3_SVE_HINT
| 2:
| << SMCCC call using FID >>
This is not safe as-is:
(1) SMCCC calls can be made in a preemptible context and preemption can
result in TIF_FOREIGN_FPSTATE being set or cleared at arbitrary
points in time. Thus checking for TIF_FOREIGN_FPSTATE provides no
guarantee.
(2) TIF_FOREIGN_FPSTATE only indicates that the live FP/SVE/SME state in
the CPU does not belong to the current task, and does not indicate
that clobbering this state is acceptable.
When the live CPU state is clobbered it is necessary to update
fpsimd_last_state.st to ensure that a subsequent context switch will
reload FP/SVE/SME state from memory rather than consuming the
clobbered state. This and the SMCCC call itself must happen in a
critical section with preemption disabled to avoid races.
(3) Live SVE/SME state can exist with TIF_SVE clear (e.g. with only
TIF_SME set), and checking TIF_SVE alone is insufficient.
Remove the broken support for the SMCCCv1.3 SVE saving hint. This is
effectively a revert of commits:
* cfa7ff959a ("arm64: smccc: Support SMCCC v1.3 SVE register saving hint")
* a7c3acca53 ("arm64: smccc: Save lr before calling __arm_smccc_sve_check()")
... leaving behind the ARM_SMCCC_VERSION_1_3 and ARM_SMCCC_1_3_SVE_HINT
definitions, since these are simply definitions from the SMCCC
specification, and the latter is used in KVM via ARM_SMCCC_CALL_HINTS.
If we want to bring this back in future, we'll probably want to handle
this logic in C where we can use all the usual FPSIMD/SVE/SME helper
functions, and that'll likely require some rework of the SMCCC code
and/or its callers.
Fixes: cfa7ff959a ("arm64: smccc: Support SMCCC v1.3 SVE register saving hint")
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: stable@vger.kernel.org
Reviewed-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20241106160448.2712997-1-mark.rutland@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
103 lines
3.0 KiB
ArmAsm
103 lines
3.0 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015, Linaro Limited
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*/
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#include <linux/linkage.h>
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#include <linux/arm-smccc.h>
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#include <asm/asm-offsets.h>
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#include <asm/assembler.h>
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.macro SMCCC instr
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\instr #0
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ldr x4, [sp]
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stp x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS]
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stp x2, x3, [x4, #ARM_SMCCC_RES_X2_OFFS]
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ldr x4, [sp, #8]
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cbz x4, 1f /* no quirk structure */
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ldr x9, [x4, #ARM_SMCCC_QUIRK_ID_OFFS]
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cmp x9, #ARM_SMCCC_QUIRK_QCOM_A6
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b.ne 1f
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str x6, [x4, ARM_SMCCC_QUIRK_STATE_OFFS]
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1: ret
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.endm
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/*
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* void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
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* unsigned long a3, unsigned long a4, unsigned long a5,
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* unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
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* struct arm_smccc_quirk *quirk)
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*/
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SYM_FUNC_START(__arm_smccc_smc)
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SMCCC smc
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SYM_FUNC_END(__arm_smccc_smc)
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EXPORT_SYMBOL(__arm_smccc_smc)
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/*
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* void arm_smccc_hvc(unsigned long a0, unsigned long a1, unsigned long a2,
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* unsigned long a3, unsigned long a4, unsigned long a5,
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* unsigned long a6, unsigned long a7, struct arm_smccc_res *res,
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* struct arm_smccc_quirk *quirk)
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*/
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SYM_FUNC_START(__arm_smccc_hvc)
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SMCCC hvc
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SYM_FUNC_END(__arm_smccc_hvc)
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EXPORT_SYMBOL(__arm_smccc_hvc)
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.macro SMCCC_1_2 instr
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/* Save `res` and free a GPR that won't be clobbered */
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stp x1, x19, [sp, #-16]!
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/* Ensure `args` won't be clobbered while loading regs in next step */
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mov x19, x0
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/* Load the registers x0 - x17 from the struct arm_smccc_1_2_regs */
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ldp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
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ldp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]
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ldp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]
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ldp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]
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ldp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
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ldp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]
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ldp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]
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ldp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]
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ldp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
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\instr #0
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/* Load the `res` from the stack */
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ldr x19, [sp]
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/* Store the registers x0 - x17 into the result structure */
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stp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
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stp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]
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stp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]
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stp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]
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stp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
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stp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]
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stp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]
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stp x14, x15, [x19, #ARM_SMCCC_1_2_REGS_X14_OFFS]
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stp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
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/* Restore original x19 */
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ldp xzr, x19, [sp], #16
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ret
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.endm
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/*
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* void arm_smccc_1_2_hvc(const struct arm_smccc_1_2_regs *args,
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* struct arm_smccc_1_2_regs *res);
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*/
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SYM_FUNC_START(arm_smccc_1_2_hvc)
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SMCCC_1_2 hvc
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SYM_FUNC_END(arm_smccc_1_2_hvc)
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EXPORT_SYMBOL(arm_smccc_1_2_hvc)
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/*
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* void arm_smccc_1_2_smc(const struct arm_smccc_1_2_regs *args,
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* struct arm_smccc_1_2_regs *res);
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*/
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SYM_FUNC_START(arm_smccc_1_2_smc)
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SMCCC_1_2 smc
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SYM_FUNC_END(arm_smccc_1_2_smc)
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EXPORT_SYMBOL(arm_smccc_1_2_smc)
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