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Add documentation for the device tree bindings of the MDIO mux of Amlogic g12a SoC family Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net>
49 lines
1.3 KiB
Plaintext
49 lines
1.3 KiB
Plaintext
Properties for the MDIO bus multiplexer/glue of Amlogic G12a SoC family.
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This is a special case of a MDIO bus multiplexer. It allows to choose between
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the internal mdio bus leading to the embedded 10/100 PHY or the external
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MDIO bus.
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Required properties in addition to the generic multiplexer properties:
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- compatible : amlogic,g12a-mdio-mux
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- reg: physical address and length of the multiplexer/glue registers
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- clocks: list of clock phandle, one for each entry clock-names.
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- clock-names: should contain the following:
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* "pclk" : peripheral clock.
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* "clkin0" : platform crytal
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* "clkin1" : SoC 50MHz MPLL
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Example :
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mdio_mux: mdio-multiplexer@4c000 {
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compatible = "amlogic,g12a-mdio-mux";
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reg = <0x0 0x4c000 0x0 0xa4>;
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clocks = <&clkc CLKID_ETH_PHY>,
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<&xtal>,
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<&clkc CLKID_MPLL_5OM>;
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clock-names = "pclk", "clkin0", "clkin1";
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mdio-parent-bus = <&mdio0>;
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#address-cells = <1>;
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#size-cells = <0>;
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ext_mdio: mdio@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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int_mdio: mdio@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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internal_ephy: ethernet-phy@8 {
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compatible = "ethernet-phy-id0180.3301",
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"ethernet-phy-ieee802.3-c22";
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <8>;
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max-speed = <100>;
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};
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};
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};
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