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99c6b20edf
This driver has been implicitly relying on kmalloc alignment to be sufficient for DMA. This may no longer be the case with upcoming arm64 changes. This patch changes it to explicitly request DMA alignment from the Crypto API. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
289 lines
7.3 KiB
C
289 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* AMD Cryptographic Coprocessor (CCP) AES XTS crypto API support
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*
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* Copyright (C) 2013,2017 Advanced Micro Devices, Inc.
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*
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* Author: Gary R Hook <gary.hook@amd.com>
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* Author: Tom Lendacky <thomas.lendacky@amd.com>
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*/
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/delay.h>
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#include <linux/scatterlist.h>
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#include <crypto/aes.h>
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#include <crypto/xts.h>
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#include <crypto/internal/skcipher.h>
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#include <crypto/scatterwalk.h>
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#include "ccp-crypto.h"
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struct ccp_aes_xts_def {
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const char *name;
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const char *drv_name;
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};
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static const struct ccp_aes_xts_def aes_xts_algs[] = {
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{
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.name = "xts(aes)",
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.drv_name = "xts-aes-ccp",
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},
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};
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struct ccp_unit_size_map {
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unsigned int size;
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u32 value;
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};
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static struct ccp_unit_size_map xts_unit_sizes[] = {
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{
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.size = 16,
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.value = CCP_XTS_AES_UNIT_SIZE_16,
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},
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{
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.size = 512,
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.value = CCP_XTS_AES_UNIT_SIZE_512,
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},
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{
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.size = 1024,
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.value = CCP_XTS_AES_UNIT_SIZE_1024,
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},
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{
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.size = 2048,
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.value = CCP_XTS_AES_UNIT_SIZE_2048,
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},
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{
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.size = 4096,
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.value = CCP_XTS_AES_UNIT_SIZE_4096,
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},
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};
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static int ccp_aes_xts_complete(struct crypto_async_request *async_req, int ret)
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{
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struct skcipher_request *req = skcipher_request_cast(async_req);
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struct ccp_aes_req_ctx *rctx = skcipher_request_ctx_dma(req);
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if (ret)
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return ret;
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memcpy(req->iv, rctx->iv, AES_BLOCK_SIZE);
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return 0;
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}
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static int ccp_aes_xts_setkey(struct crypto_skcipher *tfm, const u8 *key,
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unsigned int key_len)
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{
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struct ccp_ctx *ctx = crypto_skcipher_ctx_dma(tfm);
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unsigned int ccpversion = ccp_version();
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int ret;
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ret = xts_verify_key(tfm, key, key_len);
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if (ret)
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return ret;
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/* Version 3 devices support 128-bit keys; version 5 devices can
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* accommodate 128- and 256-bit keys.
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*/
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switch (key_len) {
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case AES_KEYSIZE_128 * 2:
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memcpy(ctx->u.aes.key, key, key_len);
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break;
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case AES_KEYSIZE_256 * 2:
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if (ccpversion > CCP_VERSION(3, 0))
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memcpy(ctx->u.aes.key, key, key_len);
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break;
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}
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ctx->u.aes.key_len = key_len / 2;
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sg_init_one(&ctx->u.aes.key_sg, ctx->u.aes.key, key_len);
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return crypto_skcipher_setkey(ctx->u.aes.tfm_skcipher, key, key_len);
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}
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static int ccp_aes_xts_crypt(struct skcipher_request *req,
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unsigned int encrypt)
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{
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struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
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struct ccp_ctx *ctx = crypto_skcipher_ctx_dma(tfm);
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struct ccp_aes_req_ctx *rctx = skcipher_request_ctx_dma(req);
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unsigned int ccpversion = ccp_version();
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unsigned int fallback = 0;
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unsigned int unit;
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u32 unit_size;
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int ret;
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if (!ctx->u.aes.key_len)
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return -EINVAL;
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if (!req->iv)
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return -EINVAL;
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/* Check conditions under which the CCP can fulfill a request. The
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* device can handle input plaintext of a length that is a multiple
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* of the unit_size, bug the crypto implementation only supports
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* the unit_size being equal to the input length. This limits the
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* number of scenarios we can handle.
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*/
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unit_size = CCP_XTS_AES_UNIT_SIZE__LAST;
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for (unit = 0; unit < ARRAY_SIZE(xts_unit_sizes); unit++) {
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if (req->cryptlen == xts_unit_sizes[unit].size) {
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unit_size = unit;
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break;
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}
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}
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/* The CCP has restrictions on block sizes. Also, a version 3 device
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* only supports AES-128 operations; version 5 CCPs support both
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* AES-128 and -256 operations.
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*/
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if (unit_size == CCP_XTS_AES_UNIT_SIZE__LAST)
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fallback = 1;
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if ((ccpversion < CCP_VERSION(5, 0)) &&
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(ctx->u.aes.key_len != AES_KEYSIZE_128))
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fallback = 1;
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if ((ctx->u.aes.key_len != AES_KEYSIZE_128) &&
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(ctx->u.aes.key_len != AES_KEYSIZE_256))
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fallback = 1;
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if (fallback) {
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/* Use the fallback to process the request for any
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* unsupported unit sizes or key sizes
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*/
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skcipher_request_set_tfm(&rctx->fallback_req,
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ctx->u.aes.tfm_skcipher);
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skcipher_request_set_callback(&rctx->fallback_req,
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req->base.flags,
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req->base.complete,
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req->base.data);
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skcipher_request_set_crypt(&rctx->fallback_req, req->src,
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req->dst, req->cryptlen, req->iv);
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ret = encrypt ? crypto_skcipher_encrypt(&rctx->fallback_req) :
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crypto_skcipher_decrypt(&rctx->fallback_req);
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return ret;
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}
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memcpy(rctx->iv, req->iv, AES_BLOCK_SIZE);
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sg_init_one(&rctx->iv_sg, rctx->iv, AES_BLOCK_SIZE);
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memset(&rctx->cmd, 0, sizeof(rctx->cmd));
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INIT_LIST_HEAD(&rctx->cmd.entry);
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rctx->cmd.engine = CCP_ENGINE_XTS_AES_128;
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rctx->cmd.u.xts.type = CCP_AES_TYPE_128;
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rctx->cmd.u.xts.action = (encrypt) ? CCP_AES_ACTION_ENCRYPT
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: CCP_AES_ACTION_DECRYPT;
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rctx->cmd.u.xts.unit_size = unit_size;
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rctx->cmd.u.xts.key = &ctx->u.aes.key_sg;
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rctx->cmd.u.xts.key_len = ctx->u.aes.key_len;
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rctx->cmd.u.xts.iv = &rctx->iv_sg;
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rctx->cmd.u.xts.iv_len = AES_BLOCK_SIZE;
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rctx->cmd.u.xts.src = req->src;
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rctx->cmd.u.xts.src_len = req->cryptlen;
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rctx->cmd.u.xts.dst = req->dst;
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ret = ccp_crypto_enqueue_request(&req->base, &rctx->cmd);
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return ret;
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}
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static int ccp_aes_xts_encrypt(struct skcipher_request *req)
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{
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return ccp_aes_xts_crypt(req, 1);
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}
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static int ccp_aes_xts_decrypt(struct skcipher_request *req)
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{
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return ccp_aes_xts_crypt(req, 0);
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}
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static int ccp_aes_xts_init_tfm(struct crypto_skcipher *tfm)
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{
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struct ccp_ctx *ctx = crypto_skcipher_ctx_dma(tfm);
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struct crypto_skcipher *fallback_tfm;
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ctx->complete = ccp_aes_xts_complete;
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ctx->u.aes.key_len = 0;
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fallback_tfm = crypto_alloc_skcipher("xts(aes)", 0,
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CRYPTO_ALG_NEED_FALLBACK);
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if (IS_ERR(fallback_tfm)) {
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pr_warn("could not load fallback driver xts(aes)\n");
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return PTR_ERR(fallback_tfm);
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}
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ctx->u.aes.tfm_skcipher = fallback_tfm;
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crypto_skcipher_set_reqsize_dma(tfm,
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sizeof(struct ccp_aes_req_ctx) +
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crypto_skcipher_reqsize(fallback_tfm));
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return 0;
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}
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static void ccp_aes_xts_exit_tfm(struct crypto_skcipher *tfm)
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{
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struct ccp_ctx *ctx = crypto_skcipher_ctx_dma(tfm);
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crypto_free_skcipher(ctx->u.aes.tfm_skcipher);
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}
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static int ccp_register_aes_xts_alg(struct list_head *head,
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const struct ccp_aes_xts_def *def)
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{
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struct ccp_crypto_skcipher_alg *ccp_alg;
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struct skcipher_alg *alg;
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int ret;
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ccp_alg = kzalloc(sizeof(*ccp_alg), GFP_KERNEL);
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if (!ccp_alg)
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return -ENOMEM;
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INIT_LIST_HEAD(&ccp_alg->entry);
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alg = &ccp_alg->alg;
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snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name);
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snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
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def->drv_name);
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alg->base.cra_flags = CRYPTO_ALG_ASYNC |
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CRYPTO_ALG_ALLOCATES_MEMORY |
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CRYPTO_ALG_KERN_DRIVER_ONLY |
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CRYPTO_ALG_NEED_FALLBACK;
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alg->base.cra_blocksize = AES_BLOCK_SIZE;
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alg->base.cra_ctxsize = sizeof(struct ccp_ctx) +
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crypto_dma_padding();
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alg->base.cra_priority = CCP_CRA_PRIORITY;
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alg->base.cra_module = THIS_MODULE;
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alg->setkey = ccp_aes_xts_setkey;
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alg->encrypt = ccp_aes_xts_encrypt;
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alg->decrypt = ccp_aes_xts_decrypt;
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alg->min_keysize = AES_MIN_KEY_SIZE * 2;
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alg->max_keysize = AES_MAX_KEY_SIZE * 2;
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alg->ivsize = AES_BLOCK_SIZE;
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alg->init = ccp_aes_xts_init_tfm;
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alg->exit = ccp_aes_xts_exit_tfm;
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ret = crypto_register_skcipher(alg);
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if (ret) {
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pr_err("%s skcipher algorithm registration error (%d)\n",
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alg->base.cra_name, ret);
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kfree(ccp_alg);
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return ret;
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}
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list_add(&ccp_alg->entry, head);
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return 0;
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}
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int ccp_register_aes_xts_algs(struct list_head *head)
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{
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int i, ret;
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for (i = 0; i < ARRAY_SIZE(aes_xts_algs); i++) {
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ret = ccp_register_aes_xts_alg(head, &aes_xts_algs[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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