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Instantiate the L2 cache from DT. Indicate in DT where the cache control register is so that it is possible to enable/disable write through on the CPU. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
17 lines
414 B
Plaintext
17 lines
414 B
Plaintext
* Marvell Feroceon Cache
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Required properties:
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- compatible : Should be either "marvell,feroceon-cache" or
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"marvell,kirkwood-cache".
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Optional properties:
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- reg : Address of the L2 cache control register. Mandatory for
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"marvell,kirkwood-cache", not used by "marvell,feroceon-cache"
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Example:
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l2: l2-cache@20128 {
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compatible = "marvell,kirkwood-cache";
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reg = <0x20128 0x4>;
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};
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