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ab4382d274
The serial drivers are really just tty drivers, so move them to drivers/tty/ to make things a bit neater overall. This is part of the tty/serial driver movement proceedure as proposed by Arnd Bergmann and approved by everyone involved a number of months ago. Cc: Arnd Bergmann <arnd@arndb.de> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Rogier Wolff <R.E.Wolff@bitwizard.nl> Cc: Michael H. Warfield <mhw@wittsend.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
285 lines
9.4 KiB
C
285 lines
9.4 KiB
C
/*
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* zs.h: Definitions for the DECstation Z85C30 serial driver.
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*
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* Adapted from drivers/sbus/char/sunserial.h by Paul Mackerras.
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* Adapted from drivers/macintosh/macserial.h by Harald Koerfgen.
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*
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* Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 2004, 2005, 2007 Maciej W. Rozycki
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*/
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#ifndef _SERIAL_ZS_H
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#define _SERIAL_ZS_H
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#ifdef __KERNEL__
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#define ZS_NUM_REGS 16
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/*
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* This is our internal structure for each serial port's state.
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*/
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struct zs_port {
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struct zs_scc *scc; /* Containing SCC. */
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struct uart_port port; /* Underlying UART. */
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int clk_mode; /* May be 1, 16, 32, or 64. */
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unsigned int tty_break; /* Set on BREAK condition. */
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int tx_stopped; /* Output is suspended. */
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unsigned int mctrl; /* State of modem lines. */
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u8 brk; /* BREAK state from RR0. */
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u8 regs[ZS_NUM_REGS]; /* Channel write registers. */
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};
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/*
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* Per-SCC state for locking and the interrupt handler.
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*/
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struct zs_scc {
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struct zs_port zport[2];
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spinlock_t zlock;
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atomic_t irq_guard;
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int initialised;
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};
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#endif /* __KERNEL__ */
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/*
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* Conversion routines to/from brg time constants from/to bits per second.
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*/
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#define ZS_BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
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#define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
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/*
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* The Zilog register set.
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*/
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/* Write Register 0 (Command) */
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#define R0 0 /* Register selects */
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#define R1 1
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#define R2 2
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#define R3 3
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#define R4 4
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#define R5 5
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#define R6 6
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#define R7 7
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#define R8 8
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#define R9 9
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#define R10 10
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#define R11 11
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#define R12 12
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#define R13 13
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#define R14 14
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#define R15 15
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#define NULLCODE 0 /* Null Code */
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#define POINT_HIGH 0x8 /* Select upper half of registers */
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#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
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#define SEND_ABORT 0x18 /* HDLC Abort */
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#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
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#define RES_Tx_P 0x28 /* Reset TxINT Pending */
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#define ERR_RES 0x30 /* Error Reset */
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#define RES_H_IUS 0x38 /* Reset highest IUS */
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#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
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#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
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#define RES_EOM_L 0xC0 /* Reset EOM latch */
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/* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
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#define EXT_INT_ENAB 0x1 /* Ext Int Enable */
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#define TxINT_ENAB 0x2 /* Tx Int Enable */
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#define PAR_SPEC 0x4 /* Parity is special condition */
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#define RxINT_DISAB 0 /* Rx Int Disable */
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#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
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#define RxINT_ALL 0x10 /* Int on all Rx Characters or error */
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#define RxINT_ERR 0x18 /* Int on error only */
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#define RxINT_MASK 0x18
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#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
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#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
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#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
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/* Write Register 2 (Interrupt Vector) */
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/* Write Register 3 (Receive Parameters and Control) */
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#define RxENABLE 0x1 /* Rx Enable */
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#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
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#define ADD_SM 0x4 /* Address Search Mode (SDLC) */
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#define RxCRC_ENAB 0x8 /* Rx CRC Enable */
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#define ENT_HM 0x10 /* Enter Hunt Mode */
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#define AUTO_ENAB 0x20 /* Auto Enables */
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#define Rx5 0x0 /* Rx 5 Bits/Character */
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#define Rx7 0x40 /* Rx 7 Bits/Character */
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#define Rx6 0x80 /* Rx 6 Bits/Character */
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#define Rx8 0xc0 /* Rx 8 Bits/Character */
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#define RxNBITS_MASK 0xc0
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/* Write Register 4 (Transmit/Receive Miscellaneous Parameters and Modes) */
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#define PAR_ENA 0x1 /* Parity Enable */
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#define PAR_EVEN 0x2 /* Parity Even/Odd* */
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#define SYNC_ENAB 0 /* Sync Modes Enable */
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#define SB1 0x4 /* 1 stop bit/char */
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#define SB15 0x8 /* 1.5 stop bits/char */
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#define SB2 0xc /* 2 stop bits/char */
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#define SB_MASK 0xc
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#define MONSYNC 0 /* 8 Bit Sync character */
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#define BISYNC 0x10 /* 16 bit sync character */
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#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
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#define EXTSYNC 0x30 /* External Sync Mode */
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#define X1CLK 0x0 /* x1 clock mode */
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#define X16CLK 0x40 /* x16 clock mode */
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#define X32CLK 0x80 /* x32 clock mode */
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#define X64CLK 0xc0 /* x64 clock mode */
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#define XCLK_MASK 0xc0
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/* Write Register 5 (Transmit Parameters and Controls) */
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#define TxCRC_ENAB 0x1 /* Tx CRC Enable */
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#define RTS 0x2 /* RTS */
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#define SDLC_CRC 0x4 /* SDLC/CRC-16 */
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#define TxENAB 0x8 /* Tx Enable */
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#define SND_BRK 0x10 /* Send Break */
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#define Tx5 0x0 /* Tx 5 bits (or less)/character */
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#define Tx7 0x20 /* Tx 7 bits/character */
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#define Tx6 0x40 /* Tx 6 bits/character */
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#define Tx8 0x60 /* Tx 8 bits/character */
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#define TxNBITS_MASK 0x60
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#define DTR 0x80 /* DTR */
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/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
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/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
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/* Write Register 8 (Transmit Buffer) */
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/* Write Register 9 (Master Interrupt Control) */
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#define VIS 1 /* Vector Includes Status */
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#define NV 2 /* No Vector */
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#define DLC 4 /* Disable Lower Chain */
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#define MIE 8 /* Master Interrupt Enable */
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#define STATHI 0x10 /* Status high */
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#define SOFTACK 0x20 /* Software Interrupt Acknowledge */
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#define NORESET 0 /* No reset on write to R9 */
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#define CHRB 0x40 /* Reset channel B */
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#define CHRA 0x80 /* Reset channel A */
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#define FHWRES 0xc0 /* Force hardware reset */
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/* Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) */
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#define BIT6 1 /* 6 bit/8bit sync */
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#define LOOPMODE 2 /* SDLC Loop mode */
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#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
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#define MARKIDLE 8 /* Mark/flag on idle */
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#define GAOP 0x10 /* Go active on poll */
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#define NRZ 0 /* NRZ mode */
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#define NRZI 0x20 /* NRZI mode */
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#define FM1 0x40 /* FM1 (transition = 1) */
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#define FM0 0x60 /* FM0 (transition = 0) */
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#define CRCPS 0x80 /* CRC Preset I/O */
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/* Write Register 11 (Clock Mode Control) */
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#define TRxCXT 0 /* TRxC = Xtal output */
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#define TRxCTC 1 /* TRxC = Transmit clock */
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#define TRxCBR 2 /* TRxC = BR Generator Output */
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#define TRxCDP 3 /* TRxC = DPLL output */
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#define TRxCOI 4 /* TRxC O/I */
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#define TCRTxCP 0 /* Transmit clock = RTxC pin */
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#define TCTRxCP 8 /* Transmit clock = TRxC pin */
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#define TCBR 0x10 /* Transmit clock = BR Generator output */
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#define TCDPLL 0x18 /* Transmit clock = DPLL output */
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#define RCRTxCP 0 /* Receive clock = RTxC pin */
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#define RCTRxCP 0x20 /* Receive clock = TRxC pin */
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#define RCBR 0x40 /* Receive clock = BR Generator output */
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#define RCDPLL 0x60 /* Receive clock = DPLL output */
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#define RTxCX 0x80 /* RTxC Xtal/No Xtal */
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/* Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) */
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/* Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) */
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/* Write Register 14 (Miscellaneous Control Bits) */
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#define BRENABL 1 /* Baud rate generator enable */
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#define BRSRC 2 /* Baud rate generator source */
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#define DTRREQ 4 /* DTR/Request function */
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#define AUTOECHO 8 /* Auto Echo */
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#define LOOPBAK 0x10 /* Local loopback */
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#define SEARCH 0x20 /* Enter search mode */
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#define RMC 0x40 /* Reset missing clock */
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#define DISDPLL 0x60 /* Disable DPLL */
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#define SSBR 0x80 /* Set DPLL source = BR generator */
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#define SSRTxC 0xa0 /* Set DPLL source = RTxC */
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#define SFMM 0xc0 /* Set FM mode */
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#define SNRZI 0xe0 /* Set NRZI mode */
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/* Write Register 15 (External/Status Interrupt Control) */
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#define WR7P_EN 1 /* WR7 Prime SDLC Feature Enable */
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#define ZCIE 2 /* Zero count IE */
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#define DCDIE 8 /* DCD IE */
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#define SYNCIE 0x10 /* Sync/hunt IE */
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#define CTSIE 0x20 /* CTS IE */
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#define TxUIE 0x40 /* Tx Underrun/EOM IE */
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#define BRKIE 0x80 /* Break/Abort IE */
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/* Read Register 0 (Transmit/Receive Buffer Status and External Status) */
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#define Rx_CH_AV 0x1 /* Rx Character Available */
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#define ZCOUNT 0x2 /* Zero count */
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#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
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#define DCD 0x8 /* DCD */
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#define SYNC_HUNT 0x10 /* Sync/hunt */
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#define CTS 0x20 /* CTS */
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#define TxEOM 0x40 /* Tx underrun */
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#define BRK_ABRT 0x80 /* Break/Abort */
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/* Read Register 1 (Special Receive Condition Status) */
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#define ALL_SNT 0x1 /* All sent */
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/* Residue Data for 8 Rx bits/char programmed */
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#define RES3 0x8 /* 0/3 */
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#define RES4 0x4 /* 0/4 */
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#define RES5 0xc /* 0/5 */
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#define RES6 0x2 /* 0/6 */
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#define RES7 0xa /* 0/7 */
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#define RES8 0x6 /* 0/8 */
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#define RES18 0xe /* 1/8 */
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#define RES28 0x0 /* 2/8 */
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/* Special Rx Condition Interrupts */
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#define PAR_ERR 0x10 /* Parity Error */
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#define Rx_OVR 0x20 /* Rx Overrun Error */
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#define FRM_ERR 0x40 /* CRC/Framing Error */
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#define END_FR 0x80 /* End of Frame (SDLC) */
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/* Read Register 2 (Interrupt Vector (WR2) -- channel A). */
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/* Read Register 2 (Modified Interrupt Vector -- channel B). */
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/* Read Register 3 (Interrupt Pending Bits -- channel A only). */
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#define CHBEXT 0x1 /* Channel B Ext/Stat IP */
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#define CHBTxIP 0x2 /* Channel B Tx IP */
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#define CHBRxIP 0x4 /* Channel B Rx IP */
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#define CHAEXT 0x8 /* Channel A Ext/Stat IP */
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#define CHATxIP 0x10 /* Channel A Tx IP */
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#define CHARxIP 0x20 /* Channel A Rx IP */
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/* Read Register 6 (SDLC FIFO Status and Byte Count LSB) */
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/* Read Register 7 (SDLC FIFO Status and Byte Count MSB) */
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/* Read Register 8 (Receive Data) */
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/* Read Register 10 (Miscellaneous Status Bits) */
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#define ONLOOP 2 /* On loop */
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#define LOOPSEND 0x10 /* Loop sending */
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#define CLK2MIS 0x40 /* Two clocks missing */
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#define CLK1MIS 0x80 /* One clock missing */
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/* Read Register 12 (Lower Byte of Baud Rate Generator Constant (WR12)) */
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/* Read Register 13 (Upper Byte of Baud Rate Generator Constant (WR13) */
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/* Read Register 15 (External/Status Interrupt Control (WR15)) */
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#endif /* _SERIAL_ZS_H */
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