Chon Ming Lee 9dd4ffdf39 drm/i915: Modify DP set clock to accomodate more eDP timings v2 ... eDP 1.4 supports 4-5 extra link rates in additional to current 2 link rate. Create a structure to store the DPLL divisor data to improve readability. v2: Fix the gen4_dpll/pch_dpll initialization to C99 designated initializers, and use a single loop for all platforms. (Jani and Daniel) Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com> [danvet: Fix up checkpatch warnings.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2013-09-04 17:34:57 +02:00
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drm	drm/i915: Modify DP set clock to accomodate more eDP timings v2	2013-09-04 17:34:57 +02:00
host1x	drm/tegra: fix up page flip flags.	2013-09-02 09:47:56 +10:00
vga	vgaarb: Fix VGA decodes changes	2013-09-03 19:17:59 +02:00
Makefile	gpu: host1x: Add host1x driver	2013-04-22 12:32:40 +02:00