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0d87c9208a
Like how pci.c exposes hif ops for the bus specific operation, expose similar hif ops table for ahb with all required functions linked to it. Many ath10k_pci_* functions are reused here in hif ops table. If something is not sharable, new functions are added for ahb and linked to hif ops table. Finally, make ath10k_ahb_probe/remove() to perform what is expected out of it. Signed-off-by: Raja Mani <rmani@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
88 lines
2.5 KiB
C
88 lines
2.5 KiB
C
/*
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* Copyright (c) 2016 Qualcomm Atheros, Inc. All rights reserved.
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* Copyright (c) 2015 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _AHB_H_
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#define _AHB_H_
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#include <linux/platform_device.h>
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struct ath10k_ahb {
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struct platform_device *pdev;
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void __iomem *mem;
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unsigned long mem_len;
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void __iomem *gcc_mem;
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void __iomem *tcsr_mem;
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int irq;
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struct clk *cmd_clk;
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struct clk *ref_clk;
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struct clk *rtc_clk;
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struct reset_control *core_cold_rst;
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struct reset_control *radio_cold_rst;
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struct reset_control *radio_warm_rst;
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struct reset_control *radio_srif_rst;
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struct reset_control *cpu_init_rst;
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};
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#ifdef CONFIG_ATH10K_AHB
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#define ATH10K_GCC_REG_BASE 0x1800000
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#define ATH10K_GCC_REG_SIZE 0x60000
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#define ATH10K_TCSR_REG_BASE 0x1900000
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#define ATH10K_TCSR_REG_SIZE 0x80000
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#define ATH10K_AHB_GCC_FEPLL_PLL_DIV 0x2f020
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#define ATH10K_AHB_WIFI_SCRATCH_5_REG 0x4f014
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#define ATH10K_AHB_WLAN_CORE_ID_REG 0x82030
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#define ATH10K_AHB_TCSR_WIFI0_GLB_CFG 0x49000
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#define ATH10K_AHB_TCSR_WIFI1_GLB_CFG 0x49004
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#define TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK BIT(25)
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#define ATH10K_AHB_TCSR_WCSS0_HALTREQ 0x52000
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#define ATH10K_AHB_TCSR_WCSS1_HALTREQ 0x52010
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#define ATH10K_AHB_TCSR_WCSS0_HALTACK 0x52004
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#define ATH10K_AHB_TCSR_WCSS1_HALTACK 0x52014
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#define ATH10K_AHB_AXI_BUS_HALT_TIMEOUT 10 /* msec */
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#define AHB_AXI_BUS_HALT_REQ 1
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#define AHB_AXI_BUS_HALT_ACK 1
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#define ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK 1
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int ath10k_ahb_init(void);
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void ath10k_ahb_exit(void);
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#else /* CONFIG_ATH10K_AHB */
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static inline int ath10k_ahb_init(void)
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{
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return 0;
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}
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static inline void ath10k_ahb_exit(void)
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{
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}
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#endif /* CONFIG_ATH10K_AHB */
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#endif /* _AHB_H_ */
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