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be1c3c1ed1
Fix several errors and warnings given by checkpatch.pl: - space between asterisk and variable name; - use of C99 // comments; - using simple_strtol() where strict_strtol() could be used. In addition to these changes, also do the following: - properly indent the code; - remove space after the type cast's closing parenthesis; - replace numeric literals/expressions with the matching macros; - replace spaces after the macro name with tabs in the #define directives, and sometimes insert spaces there; - fix typos/errors, capitalize acronyms, etc. in the comments; - make the multi-line comment style consistent with the kernel style elsewhere by adding empty first line; - update MontaVista copyright; - remove Pete Popov's old email address... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
110 lines
3.7 KiB
C
110 lines
3.7 KiB
C
/*
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* Copyright 2002, 2008 MontaVista Software Inc.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-pb1x00/pb1100.h>
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void board_reset(void)
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{
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/* Hit BCSR.RST_VDDI[SOFT_RESET] */
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au_writel(0x00000000, PB1100_RST_VDDI);
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}
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void __init board_setup(void)
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{
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volatile void __iomem *base = (volatile void __iomem *)0xac000000UL;
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/* Set AUX clock to 12 MHz * 8 = 96 MHz */
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au_writel(8, SYS_AUXPLL);
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au_writel(0, SYS_PININPUTEN);
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udelay(100);
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#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
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{
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u32 pin_func, sys_freqctrl, sys_clksrc;
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/* Configure pins GPIO[14:9] as GPIO */
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pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
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/* Zero and disable FREQ2 */
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sys_freqctrl = au_readl(SYS_FREQCTRL0);
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sys_freqctrl &= ~0xFFF00000;
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au_writel(sys_freqctrl, SYS_FREQCTRL0);
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/* Zero and disable USBH/USBD/IrDA clock */
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sys_clksrc = au_readl(SYS_CLKSRC);
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sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
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au_writel(sys_clksrc, SYS_CLKSRC);
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sys_freqctrl = au_readl(SYS_FREQCTRL0);
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sys_freqctrl &= ~0xFFF00000;
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sys_clksrc = au_readl(SYS_CLKSRC);
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sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
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/* FREQ2 = aux / 2 = 48 MHz */
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sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
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SYS_FC_FE2 | SYS_FC_FS2;
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au_writel(sys_freqctrl, SYS_FREQCTRL0);
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/*
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* Route 48 MHz FREQ2 into USBH/USBD/IrDA
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*/
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sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MIR_BIT;
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au_writel(sys_clksrc, SYS_CLKSRC);
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/* Setup the static bus controller */
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au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
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au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
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au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
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/*
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* Get USB Functionality pin state (device vs host drive pins).
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*/
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pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
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/* 2nd USB port is USB host. */
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pin_func |= SYS_PF_USB;
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au_writel(pin_func, SYS_PINFUNC);
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}
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#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
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/* Enable sys bus clock divider when IDLE state or no bus activity. */
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au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
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/* Enable the RTC if not already enabled. */
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if (!(readb(base + 0x28) & 0x20)) {
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writeb(readb(base + 0x28) | 0x20, base + 0x28);
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au_sync();
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}
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/* Put the clock in BCD mode. */
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if (readb(base + 0x2C) & 0x4) { /* reg B */
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writeb(readb(base + 0x2c) & ~0x4, base + 0x2c);
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au_sync();
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}
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}
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