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9d35dc3006
Current C-SKY ASID mechanism is from mips and it doesn't work well with multi-cores. ASID per core mechanism is not suitable for C-SKY SMP tlb maintain operations, eg: tlbi.vas need share the same asid in all processors and it'll invalid the tlb entry in all cores with the same asid. This patch is prepare for new ASID mechanism. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de>
44 lines
783 B
C
44 lines
783 B
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/setup.h>
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void flush_tlb_all(void)
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{
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tlb_invalid_all();
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}
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void flush_tlb_mm(struct mm_struct *mm)
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{
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tlb_invalid_all();
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}
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void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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tlb_invalid_all();
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}
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void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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tlb_invalid_all();
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}
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
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{
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tlb_invalid_all();
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}
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void flush_tlb_one(unsigned long addr)
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{
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tlb_invalid_all();
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}
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EXPORT_SYMBOL(flush_tlb_one);
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