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078e548af9
After commit 0edb555a65 ("platform: Make platform_driver::remove()
return void") .remove() is (again) the right callback to implement for
platform drivers.
Convert all platform drivers below drivers/mmc to use .remove(), with
the eventual goal to drop struct platform_driver::remove_new(). As
.remove() and .remove_new() have the same prototypes, conversion is done
by just changing the structure member name in the driver initializer.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Link: https://lore.kernel.org/r/20240927145832.754697-2-u.kleine-koenig@baylibre.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
130 lines
3.4 KiB
C
130 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* StarFive Designware Mobile Storage Host Controller Driver
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*
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* Copyright (c) 2022 StarFive Technology Co., Ltd.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mmc/host.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "dw_mmc.h"
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#include "dw_mmc-pltfm.h"
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#define ALL_INT_CLR 0x1ffff
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#define MAX_DELAY_CHAIN 32
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#define STARFIVE_SMPL_PHASE GENMASK(20, 16)
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static void dw_mci_starfive_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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{
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int ret;
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unsigned int clock;
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if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) {
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clock = (ios->clock > 50000000 && ios->clock <= 52000000) ? 100000000 : ios->clock;
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ret = clk_set_rate(host->ciu_clk, clock);
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if (ret)
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dev_dbg(host->dev, "Use an external frequency divider %uHz\n", ios->clock);
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host->bus_hz = clk_get_rate(host->ciu_clk);
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} else {
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dev_dbg(host->dev, "Using the internal divider\n");
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}
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}
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static void dw_mci_starfive_set_sample_phase(struct dw_mci *host, u32 smpl_phase)
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{
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/* change driver phase and sample phase */
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u32 reg_value = mci_readl(host, UHS_REG_EXT);
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/* In UHS_REG_EXT, only 5 bits valid in DRV_PHASE and SMPL_PHASE */
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reg_value &= ~STARFIVE_SMPL_PHASE;
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reg_value |= FIELD_PREP(STARFIVE_SMPL_PHASE, smpl_phase);
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mci_writel(host, UHS_REG_EXT, reg_value);
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/* We should delay 1ms wait for timing setting finished. */
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mdelay(1);
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}
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static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot,
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u32 opcode)
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{
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static const int grade = MAX_DELAY_CHAIN;
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struct dw_mci *host = slot->host;
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int smpl_phase, smpl_raise = -1, smpl_fall = -1;
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int ret;
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for (smpl_phase = 0; smpl_phase < grade; smpl_phase++) {
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dw_mci_starfive_set_sample_phase(host, smpl_phase);
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mci_writel(host, RINTSTS, ALL_INT_CLR);
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ret = mmc_send_tuning(slot->mmc, opcode, NULL);
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if (!ret && smpl_raise < 0) {
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smpl_raise = smpl_phase;
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} else if (ret && smpl_raise >= 0) {
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smpl_fall = smpl_phase - 1;
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break;
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}
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}
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if (smpl_phase >= grade)
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smpl_fall = grade - 1;
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if (smpl_raise < 0) {
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smpl_phase = 0;
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dev_err(host->dev, "No valid delay chain! use default\n");
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ret = -EINVAL;
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goto out;
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}
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smpl_phase = (smpl_raise + smpl_fall) / 2;
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dev_dbg(host->dev, "Found valid delay chain! use it [delay=%d]\n", smpl_phase);
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ret = 0;
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out:
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dw_mci_starfive_set_sample_phase(host, smpl_phase);
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mci_writel(host, RINTSTS, ALL_INT_CLR);
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return ret;
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}
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static const struct dw_mci_drv_data starfive_data = {
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.common_caps = MMC_CAP_CMD23,
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.set_ios = dw_mci_starfive_set_ios,
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.execute_tuning = dw_mci_starfive_execute_tuning,
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};
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static const struct of_device_id dw_mci_starfive_match[] = {
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{ .compatible = "starfive,jh7110-mmc",
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.data = &starfive_data },
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{},
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};
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MODULE_DEVICE_TABLE(of, dw_mci_starfive_match);
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static int dw_mci_starfive_probe(struct platform_device *pdev)
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{
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return dw_mci_pltfm_register(pdev, &starfive_data);
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}
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static struct platform_driver dw_mci_starfive_driver = {
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.probe = dw_mci_starfive_probe,
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.remove = dw_mci_pltfm_remove,
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.driver = {
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.name = "dwmmc_starfive",
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.probe_type = PROBE_PREFER_ASYNCHRONOUS,
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.of_match_table = dw_mci_starfive_match,
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},
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};
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module_platform_driver(dw_mci_starfive_driver);
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MODULE_DESCRIPTION("StarFive JH7110 Specific DW-MSHC Driver Extension");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:dwmmc_starfive");
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