Doug Anderson 9c030ea70b clk: rockchip: change pll rate without a clk-notifier ... The Rockchip PLL code switches into slow mode (AKA bypass more AKA 24MHz mode) before actually changing the PLL. This keeps anyone from using the PLL while it's changing. However, in all known Rockchip SoCs nobody should ever see the 24MHz when changing the PLL supplying the armclk because we should reparent children to an alternate (faster than 24MHz) PLL. One problem is that the code to switch to an alternate parent was running in PRE_RATE_CHANGE. ...and the code to switch to slow mode was _also_ running in PRE_RATE_CHANGE. That meant there was no real guarantee that we would switch to an alternate parent before switching to 24MHz mode. Let's move the switch to "slow mode" straight into rockchip_rk3066_pll_set_rate(). That means we're guaranteed that the 24MHz is really a last-resort. Note that without this change on real systems we were the code to switch to an alternate parent at 24MHz. In some older versions of that code we'd appy a (temporary) / 5 to the 24MHz causing us to run at 4.8MHz. That wasn't enough to service USB interrupts in some cases and could lead to a system hang. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>		2014-09-27 17:57:04 +02:00
..
clk-pll.c	clk: rockchip: change pll rate without a clk-notifier	2014-09-27 17:57:04 +02:00
clk-rk3188.c	clk: rockchip: also protect hclk_peri as critical	2014-09-10 10:42:02 -07:00
clk-rk3288.c	Merge branch 'clk-next-rockchip' into clk-next	2014-09-25 15:48:04 -07:00
clk-rockchip.c	clk: rockchip: fix function type for CLK_OF_DECLARE	2014-05-20 14:25:22 -05:00
clk.c	clk: rockchip: protect critical clocks from getting disabled	2014-09-02 15:03:18 -07:00
clk.h	clk: rockchip: protect critical clocks from getting disabled	2014-09-02 15:03:18 -07:00
Makefile	clk: rockchip: add clock controller for rk3288	2014-07-13 12:17:10 -07:00
softrst.c	clk: rockchip: add reset controller	2014-07-13 12:17:07 -07:00