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283bab9809
Both functions call init_intel_cacheinfo() which computes L2 and L3 cache sizes from CPUID(4). But then they also call cpu_detect_cache_sizes() a bit later which computes ->x86_tlbsize and L2 size from CPUID(80000006). However, the latter call is not needed because - on these CPUs, CPUID(80000006).EBX for ->x86_tlbsize is reserved - CPUID(80000006).ECX for the L2 size has the same result as CPUID(4) Therefore, remove the latter call to simplify the code. [ bp: Rewrite commit message. ] Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com> Signed-off-by: Borislav Petkov <bp@suse.de> Link: https://lkml.kernel.org/r/1579075257-6985-1-git-send-email-TonyWWang-oc@zhaoxin.com
133 lines
3.1 KiB
C
133 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/sched.h>
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#include <linux/sched/clock.h>
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#include <asm/cpufeature.h>
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#include "cpu.h"
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#define MSR_ZHAOXIN_FCR57 0x00001257
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#define ACE_PRESENT (1 << 6)
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#define ACE_ENABLED (1 << 7)
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#define ACE_FCR (1 << 7) /* MSR_ZHAOXIN_FCR */
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#define RNG_PRESENT (1 << 2)
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#define RNG_ENABLED (1 << 3)
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#define RNG_ENABLE (1 << 8) /* MSR_ZHAOXIN_RNG */
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static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
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{
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u32 lo, hi;
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/* Test for Extended Feature Flags presence */
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if (cpuid_eax(0xC0000000) >= 0xC0000001) {
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u32 tmp = cpuid_edx(0xC0000001);
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/* Enable ACE unit, if present and disabled */
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if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
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rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
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/* Enable ACE unit */
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lo |= ACE_FCR;
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wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
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pr_info("CPU: Enabled ACE h/w crypto\n");
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}
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/* Enable RNG unit, if present and disabled */
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if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
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rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
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/* Enable RNG unit */
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lo |= RNG_ENABLE;
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wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
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pr_info("CPU: Enabled h/w RNG\n");
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}
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/*
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* Store Extended Feature Flags as word 5 of the CPU
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* capability bit array
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*/
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c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
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}
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if (c->x86 >= 0x6)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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}
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static void early_init_zhaoxin(struct cpuinfo_x86 *c)
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{
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if (c->x86 >= 0x6)
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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#ifdef CONFIG_X86_64
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set_cpu_cap(c, X86_FEATURE_SYSENTER32);
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#endif
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if (c->x86_power & (1 << 8)) {
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
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}
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if (c->cpuid_level >= 0x00000001) {
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u32 eax, ebx, ecx, edx;
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cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
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/*
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* If HTT (EDX[28]) is set EBX[16:23] contain the number of
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* apicids which are reserved per package. Store the resulting
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* shift value for the package management code.
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*/
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if (edx & (1U << 28))
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c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
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}
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}
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static void init_zhaoxin(struct cpuinfo_x86 *c)
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{
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early_init_zhaoxin(c);
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init_intel_cacheinfo(c);
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detect_num_cpu_cores(c);
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#ifdef CONFIG_X86_32
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detect_ht(c);
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#endif
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if (c->cpuid_level > 9) {
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unsigned int eax = cpuid_eax(10);
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/*
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* Check for version and the number of counters
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* Version(eax[7:0]) can't be 0;
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* Counters(eax[15:8]) should be greater than 1;
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*/
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if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1))
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set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
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}
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if (c->x86 >= 0x6)
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init_zhaoxin_cap(c);
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#ifdef CONFIG_X86_64
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set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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#endif
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init_ia32_feat_ctl(c);
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}
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#ifdef CONFIG_X86_32
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static unsigned int
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zhaoxin_size_cache(struct cpuinfo_x86 *c, unsigned int size)
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{
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return size;
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}
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#endif
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static const struct cpu_dev zhaoxin_cpu_dev = {
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.c_vendor = "zhaoxin",
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.c_ident = { " Shanghai " },
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.c_early_init = early_init_zhaoxin,
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.c_init = init_zhaoxin,
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#ifdef CONFIG_X86_32
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.legacy_cache_size = zhaoxin_size_cache,
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#endif
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.c_x86_vendor = X86_VENDOR_ZHAOXIN,
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};
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cpu_dev_register(zhaoxin_cpu_dev);
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