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The ARC USB OTG Core has support for accessing ULPI tranceivers through so called ULPI viewports. Export a set of function for use with the USB OTG framework. Signed-off-by: Daniel Mack <daniel@caiaq.de> Cc: Greg Kroah-Hartman <gregkh@suse.de> Cc: David Brownell <dbrownell@users.sourceforge.net> Cc: linux-usb@vger.kernel.org Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
114 lines
3.0 KiB
C
114 lines
3.0 KiB
C
/*
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* Copyright 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
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* Copyright 2009 Daniel Mack <daniel@caiaq.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/usb/otg.h>
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#include <mach/ulpi.h>
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/* ULPIVIEW register bits */
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#define ULPIVW_WU (1 << 31) /* Wakeup */
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#define ULPIVW_RUN (1 << 30) /* read/write run */
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#define ULPIVW_WRITE (1 << 29) /* 0 = read 1 = write */
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#define ULPIVW_SS (1 << 27) /* SyncState */
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#define ULPIVW_PORT_MASK 0x07 /* Port field */
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#define ULPIVW_PORT_SHIFT 24
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#define ULPIVW_ADDR_MASK 0xff /* data address field */
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#define ULPIVW_ADDR_SHIFT 16
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#define ULPIVW_RDATA_MASK 0xff /* read data field */
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#define ULPIVW_RDATA_SHIFT 8
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#define ULPIVW_WDATA_MASK 0xff /* write data field */
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#define ULPIVW_WDATA_SHIFT 0
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static int ulpi_poll(void __iomem *view, u32 bit)
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{
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int timeout = 10000;
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while (timeout--) {
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u32 data = __raw_readl(view);
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if (!(data & bit))
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return 0;
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cpu_relax();
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};
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printk(KERN_WARNING "timeout polling for ULPI device\n");
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return -ETIMEDOUT;
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}
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static int ulpi_read(struct otg_transceiver *otg, u32 reg)
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{
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int ret;
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void __iomem *view = otg->io_priv;
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/* make sure interface is running */
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if (!(__raw_readl(view) & ULPIVW_SS)) {
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__raw_writel(ULPIVW_WU, view);
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/* wait for wakeup */
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ret = ulpi_poll(view, ULPIVW_WU);
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if (ret)
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return ret;
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}
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/* read the register */
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__raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view);
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/* wait for completion */
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ret = ulpi_poll(view, ULPIVW_RUN);
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if (ret)
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return ret;
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return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK;
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}
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static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
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{
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int ret;
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void __iomem *view = otg->io_priv;
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/* make sure the interface is running */
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if (!(__raw_readl(view) & ULPIVW_SS)) {
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__raw_writel(ULPIVW_WU, view);
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/* wait for wakeup */
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ret = ulpi_poll(view, ULPIVW_WU);
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if (ret)
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return ret;
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}
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__raw_writel((ULPIVW_RUN | ULPIVW_WRITE |
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(reg << ULPIVW_ADDR_SHIFT) |
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((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view);
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/* wait for completion */
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return ulpi_poll(view, ULPIVW_RUN);
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}
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struct otg_io_access_ops mxc_ulpi_access_ops = {
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.read = ulpi_read,
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.write = ulpi_write,
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};
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EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);
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