mirror of
https://github.com/torvalds/linux.git
synced 2024-12-18 09:02:17 +00:00
a81595729b
Add the clock binding doc for i.MXRT1050. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> [Jesse: added clocks from IMXRT1050_CLK_IPG_PDOF to IMXRT1050_CLK_DMA_MUX and moved IMXRT1050_CLK_END on] Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20220111215415.2075257-4-Mr.Bossman075@gmail.com Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
73 lines
2.5 KiB
C
73 lines
2.5 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
|
/*
|
|
* Copyright(C) 2019
|
|
* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
|
|
*/
|
|
|
|
#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H
|
|
#define __DT_BINDINGS_CLOCK_IMXRT1050_H
|
|
|
|
#define IMXRT1050_CLK_DUMMY 0
|
|
#define IMXRT1050_CLK_CKIL 1
|
|
#define IMXRT1050_CLK_CKIH 2
|
|
#define IMXRT1050_CLK_OSC 3
|
|
#define IMXRT1050_CLK_PLL2_PFD0_352M 4
|
|
#define IMXRT1050_CLK_PLL2_PFD1_594M 5
|
|
#define IMXRT1050_CLK_PLL2_PFD2_396M 6
|
|
#define IMXRT1050_CLK_PLL3_PFD0_720M 7
|
|
#define IMXRT1050_CLK_PLL3_PFD1_664_62M 8
|
|
#define IMXRT1050_CLK_PLL3_PFD2_508_24M 9
|
|
#define IMXRT1050_CLK_PLL3_PFD3_454_74M 10
|
|
#define IMXRT1050_CLK_PLL2_198M 11
|
|
#define IMXRT1050_CLK_PLL3_120M 12
|
|
#define IMXRT1050_CLK_PLL3_80M 13
|
|
#define IMXRT1050_CLK_PLL3_60M 14
|
|
#define IMXRT1050_CLK_PLL1_BYPASS 15
|
|
#define IMXRT1050_CLK_PLL2_BYPASS 16
|
|
#define IMXRT1050_CLK_PLL3_BYPASS 17
|
|
#define IMXRT1050_CLK_PLL5_BYPASS 19
|
|
#define IMXRT1050_CLK_PLL1_REF_SEL 20
|
|
#define IMXRT1050_CLK_PLL2_REF_SEL 21
|
|
#define IMXRT1050_CLK_PLL3_REF_SEL 22
|
|
#define IMXRT1050_CLK_PLL5_REF_SEL 23
|
|
#define IMXRT1050_CLK_PRE_PERIPH_SEL 24
|
|
#define IMXRT1050_CLK_PERIPH_SEL 25
|
|
#define IMXRT1050_CLK_SEMC_ALT_SEL 26
|
|
#define IMXRT1050_CLK_SEMC_SEL 27
|
|
#define IMXRT1050_CLK_USDHC1_SEL 28
|
|
#define IMXRT1050_CLK_USDHC2_SEL 29
|
|
#define IMXRT1050_CLK_LPUART_SEL 30
|
|
#define IMXRT1050_CLK_LCDIF_SEL 31
|
|
#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 32
|
|
#define IMXRT1050_CLK_VIDEO_DIV 33
|
|
#define IMXRT1050_CLK_ARM_PODF 34
|
|
#define IMXRT1050_CLK_LPUART_PODF 35
|
|
#define IMXRT1050_CLK_USDHC1_PODF 36
|
|
#define IMXRT1050_CLK_USDHC2_PODF 37
|
|
#define IMXRT1050_CLK_SEMC_PODF 38
|
|
#define IMXRT1050_CLK_AHB_PODF 39
|
|
#define IMXRT1050_CLK_LCDIF_PRED 40
|
|
#define IMXRT1050_CLK_LCDIF_PODF 41
|
|
#define IMXRT1050_CLK_USDHC1 42
|
|
#define IMXRT1050_CLK_USDHC2 43
|
|
#define IMXRT1050_CLK_LPUART1 44
|
|
#define IMXRT1050_CLK_SEMC 45
|
|
#define IMXRT1050_CLK_LCDIF_APB 46
|
|
#define IMXRT1050_CLK_PLL1_ARM 47
|
|
#define IMXRT1050_CLK_PLL2_SYS 48
|
|
#define IMXRT1050_CLK_PLL3_USB_OTG 49
|
|
#define IMXRT1050_CLK_PLL4_AUDIO 50
|
|
#define IMXRT1050_CLK_PLL5_VIDEO 51
|
|
#define IMXRT1050_CLK_PLL6_ENET 52
|
|
#define IMXRT1050_CLK_PLL7_USB_HOST 53
|
|
#define IMXRT1050_CLK_LCDIF_PIX 54
|
|
#define IMXRT1050_CLK_USBOH3 55
|
|
#define IMXRT1050_CLK_IPG_PDOF 56
|
|
#define IMXRT1050_CLK_PER_CLK_SEL 57
|
|
#define IMXRT1050_CLK_PER_PDOF 58
|
|
#define IMXRT1050_CLK_DMA 59
|
|
#define IMXRT1050_CLK_DMA_MUX 60
|
|
#define IMXRT1050_CLK_END 61
|
|
|
|
#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */
|