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99f7c229b3
This patch builds on the infrastructure introduced in the patches that allow user specification of GRU blades & chiplets for context allocation. This patch simplifies the algorithms for migrating GRU contexts between blades. No new functionality is introduced. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
780 lines
20 KiB
C
780 lines
20 KiB
C
/*
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* SN Platform GRU Driver
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*
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* FAULT HANDLER FOR GRU DETECTED TLB MISSES
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*
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* This file contains code that handles TLB misses within the GRU.
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* These misses are reported either via interrupts or user polling of
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* the user CB.
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*
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* Copyright (c) 2008 Silicon Graphics, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <linux/hugetlb.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/uaccess.h>
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#include <linux/security.h>
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#include <asm/pgtable.h>
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#include "gru.h"
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#include "grutables.h"
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#include "grulib.h"
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#include "gru_instructions.h"
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#include <asm/uv/uv_hub.h>
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/*
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* Test if a physical address is a valid GRU GSEG address
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*/
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static inline int is_gru_paddr(unsigned long paddr)
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{
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return paddr >= gru_start_paddr && paddr < gru_end_paddr;
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}
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/*
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* Find the vma of a GRU segment. Caller must hold mmap_sem.
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*/
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struct vm_area_struct *gru_find_vma(unsigned long vaddr)
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{
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struct vm_area_struct *vma;
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vma = find_vma(current->mm, vaddr);
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if (vma && vma->vm_start <= vaddr && vma->vm_ops == &gru_vm_ops)
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return vma;
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return NULL;
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}
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/*
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* Find and lock the gts that contains the specified user vaddr.
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*
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* Returns:
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* - *gts with the mmap_sem locked for read and the GTS locked.
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* - NULL if vaddr invalid OR is not a valid GSEG vaddr.
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*/
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static struct gru_thread_state *gru_find_lock_gts(unsigned long vaddr)
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{
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struct mm_struct *mm = current->mm;
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struct vm_area_struct *vma;
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struct gru_thread_state *gts = NULL;
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down_read(&mm->mmap_sem);
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vma = gru_find_vma(vaddr);
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if (vma)
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gts = gru_find_thread_state(vma, TSID(vaddr, vma));
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if (gts)
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mutex_lock(>s->ts_ctxlock);
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else
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up_read(&mm->mmap_sem);
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return gts;
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}
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static struct gru_thread_state *gru_alloc_locked_gts(unsigned long vaddr)
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{
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struct mm_struct *mm = current->mm;
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struct vm_area_struct *vma;
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struct gru_thread_state *gts = NULL;
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down_write(&mm->mmap_sem);
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vma = gru_find_vma(vaddr);
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if (vma)
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gts = gru_alloc_thread_state(vma, TSID(vaddr, vma));
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if (gts) {
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mutex_lock(>s->ts_ctxlock);
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downgrade_write(&mm->mmap_sem);
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} else {
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up_write(&mm->mmap_sem);
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}
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return gts;
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}
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/*
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* Unlock a GTS that was previously locked with gru_find_lock_gts().
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*/
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static void gru_unlock_gts(struct gru_thread_state *gts)
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{
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mutex_unlock(>s->ts_ctxlock);
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up_read(¤t->mm->mmap_sem);
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}
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/*
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* Set a CB.istatus to active using a user virtual address. This must be done
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* just prior to a TFH RESTART. The new cb.istatus is an in-cache status ONLY.
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* If the line is evicted, the status may be lost. The in-cache update
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* is necessary to prevent the user from seeing a stale cb.istatus that will
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* change as soon as the TFH restart is complete. Races may cause an
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* occasional failure to clear the cb.istatus, but that is ok.
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*/
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static void gru_cb_set_istatus_active(struct gru_instruction_bits *cbk)
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{
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if (cbk) {
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cbk->istatus = CBS_ACTIVE;
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}
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}
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/*
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* Convert a interrupt IRQ to a pointer to the GRU GTS that caused the
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* interrupt. Interrupts are always sent to a cpu on the blade that contains the
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* GRU (except for headless blades which are not currently supported). A blade
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* has N grus; a block of N consecutive IRQs is assigned to the GRUs. The IRQ
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* number uniquely identifies the GRU chiplet on the local blade that caused the
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* interrupt. Always called in interrupt context.
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*/
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static inline struct gru_state *irq_to_gru(int irq)
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{
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return &gru_base[uv_numa_blade_id()]->bs_grus[irq - IRQ_GRU];
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}
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/*
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* Read & clear a TFM
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*
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* The GRU has an array of fault maps. A map is private to a cpu
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* Only one cpu will be accessing a cpu's fault map.
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*
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* This function scans the cpu-private fault map & clears all bits that
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* are set. The function returns a bitmap that indicates the bits that
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* were cleared. Note that sense the maps may be updated asynchronously by
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* the GRU, atomic operations must be used to clear bits.
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*/
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static void get_clear_fault_map(struct gru_state *gru,
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struct gru_tlb_fault_map *imap,
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struct gru_tlb_fault_map *dmap)
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{
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unsigned long i, k;
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struct gru_tlb_fault_map *tfm;
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tfm = get_tfm_for_cpu(gru, gru_cpu_fault_map_id());
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prefetchw(tfm); /* Helps on hardware, required for emulator */
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for (i = 0; i < BITS_TO_LONGS(GRU_NUM_CBE); i++) {
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k = tfm->fault_bits[i];
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if (k)
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k = xchg(&tfm->fault_bits[i], 0UL);
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imap->fault_bits[i] = k;
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k = tfm->done_bits[i];
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if (k)
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k = xchg(&tfm->done_bits[i], 0UL);
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dmap->fault_bits[i] = k;
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}
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/*
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* Not functionally required but helps performance. (Required
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* on emulator)
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*/
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gru_flush_cache(tfm);
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}
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/*
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* Atomic (interrupt context) & non-atomic (user context) functions to
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* convert a vaddr into a physical address. The size of the page
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* is returned in pageshift.
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* returns:
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* 0 - successful
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* < 0 - error code
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* 1 - (atomic only) try again in non-atomic context
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*/
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static int non_atomic_pte_lookup(struct vm_area_struct *vma,
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unsigned long vaddr, int write,
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unsigned long *paddr, int *pageshift)
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{
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struct page *page;
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/* ZZZ Need to handle HUGE pages */
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if (is_vm_hugetlb_page(vma))
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return -EFAULT;
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*pageshift = PAGE_SHIFT;
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if (get_user_pages
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(current, current->mm, vaddr, 1, write, 0, &page, NULL) <= 0)
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return -EFAULT;
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*paddr = page_to_phys(page);
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put_page(page);
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return 0;
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}
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/*
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* atomic_pte_lookup
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*
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* Convert a user virtual address to a physical address
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* Only supports Intel large pages (2MB only) on x86_64.
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* ZZZ - hugepage support is incomplete
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*
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* NOTE: mmap_sem is already held on entry to this function. This
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* guarantees existence of the page tables.
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*/
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static int atomic_pte_lookup(struct vm_area_struct *vma, unsigned long vaddr,
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int write, unsigned long *paddr, int *pageshift)
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{
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pgd_t *pgdp;
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pmd_t *pmdp;
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pud_t *pudp;
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pte_t pte;
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pgdp = pgd_offset(vma->vm_mm, vaddr);
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if (unlikely(pgd_none(*pgdp)))
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goto err;
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pudp = pud_offset(pgdp, vaddr);
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if (unlikely(pud_none(*pudp)))
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goto err;
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pmdp = pmd_offset(pudp, vaddr);
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if (unlikely(pmd_none(*pmdp)))
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goto err;
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#ifdef CONFIG_X86_64
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if (unlikely(pmd_large(*pmdp)))
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pte = *(pte_t *) pmdp;
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else
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#endif
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pte = *pte_offset_kernel(pmdp, vaddr);
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if (unlikely(!pte_present(pte) ||
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(write && (!pte_write(pte) || !pte_dirty(pte)))))
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return 1;
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*paddr = pte_pfn(pte) << PAGE_SHIFT;
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#ifdef CONFIG_HUGETLB_PAGE
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*pageshift = is_vm_hugetlb_page(vma) ? HPAGE_SHIFT : PAGE_SHIFT;
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#else
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*pageshift = PAGE_SHIFT;
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#endif
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return 0;
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err:
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local_irq_enable();
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return 1;
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}
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static int gru_vtop(struct gru_thread_state *gts, unsigned long vaddr,
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int write, int atomic, unsigned long *gpa, int *pageshift)
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{
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struct mm_struct *mm = gts->ts_mm;
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struct vm_area_struct *vma;
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unsigned long paddr;
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int ret, ps;
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vma = find_vma(mm, vaddr);
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if (!vma)
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goto inval;
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/*
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* Atomic lookup is faster & usually works even if called in non-atomic
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* context.
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*/
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rmb(); /* Must/check ms_range_active before loading PTEs */
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ret = atomic_pte_lookup(vma, vaddr, write, &paddr, &ps);
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if (ret) {
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if (atomic)
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goto upm;
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if (non_atomic_pte_lookup(vma, vaddr, write, &paddr, &ps))
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goto inval;
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}
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if (is_gru_paddr(paddr))
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goto inval;
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paddr = paddr & ~((1UL << ps) - 1);
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*gpa = uv_soc_phys_ram_to_gpa(paddr);
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*pageshift = ps;
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return 0;
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inval:
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return -1;
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upm:
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return -2;
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}
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/*
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* Drop a TLB entry into the GRU. The fault is described by info in an TFH.
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* Input:
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* cb Address of user CBR. Null if not running in user context
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* Return:
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* 0 = dropin, exception, or switch to UPM successful
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* 1 = range invalidate active
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* < 0 = error code
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*
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*/
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static int gru_try_dropin(struct gru_thread_state *gts,
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struct gru_tlb_fault_handle *tfh,
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struct gru_instruction_bits *cbk)
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{
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int pageshift = 0, asid, write, ret, atomic = !cbk;
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unsigned long gpa = 0, vaddr = 0;
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/*
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* NOTE: The GRU contains magic hardware that eliminates races between
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* TLB invalidates and TLB dropins. If an invalidate occurs
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* in the window between reading the TFH and the subsequent TLB dropin,
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* the dropin is ignored. This eliminates the need for additional locks.
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*/
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/*
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* Error if TFH state is IDLE or FMM mode & the user issuing a UPM call.
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* Might be a hardware race OR a stupid user. Ignore FMM because FMM
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* is a transient state.
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*/
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if (tfh->status != TFHSTATUS_EXCEPTION) {
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gru_flush_cache(tfh);
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if (tfh->status != TFHSTATUS_EXCEPTION)
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goto failnoexception;
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STAT(tfh_stale_on_fault);
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}
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if (tfh->state == TFHSTATE_IDLE)
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goto failidle;
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if (tfh->state == TFHSTATE_MISS_FMM && cbk)
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goto failfmm;
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write = (tfh->cause & TFHCAUSE_TLB_MOD) != 0;
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vaddr = tfh->missvaddr;
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asid = tfh->missasid;
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if (asid == 0)
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goto failnoasid;
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rmb(); /* TFH must be cache resident before reading ms_range_active */
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/*
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* TFH is cache resident - at least briefly. Fail the dropin
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* if a range invalidate is active.
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*/
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if (atomic_read(>s->ts_gms->ms_range_active))
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goto failactive;
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ret = gru_vtop(gts, vaddr, write, atomic, &gpa, &pageshift);
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if (ret == -1)
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goto failinval;
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if (ret == -2)
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goto failupm;
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if (!(gts->ts_sizeavail & GRU_SIZEAVAIL(pageshift))) {
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gts->ts_sizeavail |= GRU_SIZEAVAIL(pageshift);
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if (atomic || !gru_update_cch(gts)) {
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gts->ts_force_cch_reload = 1;
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goto failupm;
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}
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}
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gru_cb_set_istatus_active(cbk);
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tfh_write_restart(tfh, gpa, GAA_RAM, vaddr, asid, write,
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GRU_PAGESIZE(pageshift));
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STAT(tlb_dropin);
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gru_dbg(grudev,
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"%s: tfh 0x%p, vaddr 0x%lx, asid 0x%x, ps %d, gpa 0x%lx\n",
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ret ? "non-atomic" : "atomic", tfh, vaddr, asid,
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pageshift, gpa);
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return 0;
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failnoasid:
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/* No asid (delayed unload). */
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STAT(tlb_dropin_fail_no_asid);
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gru_dbg(grudev, "FAILED no_asid tfh: 0x%p, vaddr 0x%lx\n", tfh, vaddr);
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if (!cbk)
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tfh_user_polling_mode(tfh);
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else
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gru_flush_cache(tfh);
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return -EAGAIN;
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failupm:
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/* Atomic failure switch CBR to UPM */
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tfh_user_polling_mode(tfh);
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STAT(tlb_dropin_fail_upm);
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gru_dbg(grudev, "FAILED upm tfh: 0x%p, vaddr 0x%lx\n", tfh, vaddr);
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return 1;
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failfmm:
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/* FMM state on UPM call */
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gru_flush_cache(tfh);
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STAT(tlb_dropin_fail_fmm);
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gru_dbg(grudev, "FAILED fmm tfh: 0x%p, state %d\n", tfh, tfh->state);
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return 0;
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failnoexception:
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/* TFH status did not show exception pending */
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gru_flush_cache(tfh);
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if (cbk)
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gru_flush_cache(cbk);
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STAT(tlb_dropin_fail_no_exception);
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gru_dbg(grudev, "FAILED non-exception tfh: 0x%p, status %d, state %d\n",
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tfh, tfh->status, tfh->state);
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return 0;
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failidle:
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/* TFH state was idle - no miss pending */
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gru_flush_cache(tfh);
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if (cbk)
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gru_flush_cache(cbk);
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STAT(tlb_dropin_fail_idle);
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gru_dbg(grudev, "FAILED idle tfh: 0x%p, state %d\n", tfh, tfh->state);
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return 0;
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failinval:
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/* All errors (atomic & non-atomic) switch CBR to EXCEPTION state */
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tfh_exception(tfh);
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STAT(tlb_dropin_fail_invalid);
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gru_dbg(grudev, "FAILED inval tfh: 0x%p, vaddr 0x%lx\n", tfh, vaddr);
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return -EFAULT;
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failactive:
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/* Range invalidate active. Switch to UPM iff atomic */
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if (!cbk)
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tfh_user_polling_mode(tfh);
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else
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gru_flush_cache(tfh);
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STAT(tlb_dropin_fail_range_active);
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gru_dbg(grudev, "FAILED range active: tfh 0x%p, vaddr 0x%lx\n",
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tfh, vaddr);
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return 1;
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}
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/*
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* Process an external interrupt from the GRU. This interrupt is
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* caused by a TLB miss.
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* Note that this is the interrupt handler that is registered with linux
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* interrupt handlers.
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*/
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irqreturn_t gru_intr(int irq, void *dev_id)
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{
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struct gru_state *gru;
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struct gru_tlb_fault_map imap, dmap;
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struct gru_thread_state *gts;
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struct gru_tlb_fault_handle *tfh = NULL;
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int cbrnum, ctxnum;
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STAT(intr);
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gru = irq_to_gru(irq);
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if (!gru) {
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dev_err(grudev, "GRU: invalid interrupt: cpu %d, irq %d\n",
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raw_smp_processor_id(), irq);
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return IRQ_NONE;
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}
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get_clear_fault_map(gru, &imap, &dmap);
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for_each_cbr_in_tfm(cbrnum, dmap.fault_bits) {
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complete(gru->gs_blade->bs_async_wq);
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gru_dbg(grudev, "gid %d, cbr_done %d, done %d\n",
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gru->gs_gid, cbrnum, gru->gs_blade->bs_async_wq->done);
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}
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for_each_cbr_in_tfm(cbrnum, imap.fault_bits) {
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tfh = get_tfh_by_index(gru, cbrnum);
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prefetchw(tfh); /* Helps on hdw, required for emulator */
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/*
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* When hardware sets a bit in the faultmap, it implicitly
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* locks the GRU context so that it cannot be unloaded.
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* The gts cannot change until a TFH start/writestart command
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* is issued.
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*/
|
|
ctxnum = tfh->ctxnum;
|
|
gts = gru->gs_gts[ctxnum];
|
|
|
|
/*
|
|
* This is running in interrupt context. Trylock the mmap_sem.
|
|
* If it fails, retry the fault in user context.
|
|
*/
|
|
if (!gts->ts_force_cch_reload &&
|
|
down_read_trylock(>s->ts_mm->mmap_sem)) {
|
|
gts->ustats.fmm_tlbdropin++;
|
|
gru_try_dropin(gts, tfh, NULL);
|
|
up_read(>s->ts_mm->mmap_sem);
|
|
} else {
|
|
tfh_user_polling_mode(tfh);
|
|
STAT(intr_mm_lock_failed);
|
|
}
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
|
|
static int gru_user_dropin(struct gru_thread_state *gts,
|
|
struct gru_tlb_fault_handle *tfh,
|
|
void *cb)
|
|
{
|
|
struct gru_mm_struct *gms = gts->ts_gms;
|
|
int ret;
|
|
|
|
gts->ustats.upm_tlbdropin++;
|
|
while (1) {
|
|
wait_event(gms->ms_wait_queue,
|
|
atomic_read(&gms->ms_range_active) == 0);
|
|
prefetchw(tfh); /* Helps on hdw, required for emulator */
|
|
ret = gru_try_dropin(gts, tfh, cb);
|
|
if (ret <= 0)
|
|
return ret;
|
|
STAT(call_os_wait_queue);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* This interface is called as a result of a user detecting a "call OS" bit
|
|
* in a user CB. Normally means that a TLB fault has occurred.
|
|
* cb - user virtual address of the CB
|
|
*/
|
|
int gru_handle_user_call_os(unsigned long cb)
|
|
{
|
|
struct gru_tlb_fault_handle *tfh;
|
|
struct gru_thread_state *gts;
|
|
void *cbk;
|
|
int ucbnum, cbrnum, ret = -EINVAL;
|
|
|
|
STAT(call_os);
|
|
gru_dbg(grudev, "address 0x%lx\n", cb);
|
|
|
|
/* sanity check the cb pointer */
|
|
ucbnum = get_cb_number((void *)cb);
|
|
if ((cb & (GRU_HANDLE_STRIDE - 1)) || ucbnum >= GRU_NUM_CB)
|
|
return -EINVAL;
|
|
|
|
gts = gru_find_lock_gts(cb);
|
|
if (!gts)
|
|
return -EINVAL;
|
|
|
|
if (ucbnum >= gts->ts_cbr_au_count * GRU_CBR_AU_SIZE)
|
|
goto exit;
|
|
|
|
gru_check_context_placement(gts);
|
|
|
|
/*
|
|
* CCH may contain stale data if ts_force_cch_reload is set.
|
|
*/
|
|
if (gts->ts_gru && gts->ts_force_cch_reload) {
|
|
gts->ts_force_cch_reload = 0;
|
|
gru_update_cch(gts);
|
|
}
|
|
|
|
ret = -EAGAIN;
|
|
cbrnum = thread_cbr_number(gts, ucbnum);
|
|
if (gts->ts_gru) {
|
|
tfh = get_tfh_by_index(gts->ts_gru, cbrnum);
|
|
cbk = get_gseg_base_address_cb(gts->ts_gru->gs_gru_base_vaddr,
|
|
gts->ts_ctxnum, ucbnum);
|
|
ret = gru_user_dropin(gts, tfh, cbk);
|
|
}
|
|
exit:
|
|
gru_unlock_gts(gts);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Fetch the exception detail information for a CB that terminated with
|
|
* an exception.
|
|
*/
|
|
int gru_get_exception_detail(unsigned long arg)
|
|
{
|
|
struct control_block_extended_exc_detail excdet;
|
|
struct gru_control_block_extended *cbe;
|
|
struct gru_thread_state *gts;
|
|
int ucbnum, cbrnum, ret;
|
|
|
|
STAT(user_exception);
|
|
if (copy_from_user(&excdet, (void __user *)arg, sizeof(excdet)))
|
|
return -EFAULT;
|
|
|
|
gru_dbg(grudev, "address 0x%lx\n", excdet.cb);
|
|
gts = gru_find_lock_gts(excdet.cb);
|
|
if (!gts)
|
|
return -EINVAL;
|
|
|
|
ucbnum = get_cb_number((void *)excdet.cb);
|
|
if (ucbnum >= gts->ts_cbr_au_count * GRU_CBR_AU_SIZE) {
|
|
ret = -EINVAL;
|
|
} else if (gts->ts_gru) {
|
|
cbrnum = thread_cbr_number(gts, ucbnum);
|
|
cbe = get_cbe_by_index(gts->ts_gru, cbrnum);
|
|
gru_flush_cache(cbe); /* CBE not coherent */
|
|
excdet.opc = cbe->opccpy;
|
|
excdet.exopc = cbe->exopccpy;
|
|
excdet.ecause = cbe->ecause;
|
|
excdet.exceptdet0 = cbe->idef1upd;
|
|
excdet.exceptdet1 = cbe->idef3upd;
|
|
excdet.cbrstate = cbe->cbrstate;
|
|
excdet.cbrexecstatus = cbe->cbrexecstatus;
|
|
gru_flush_cache(cbe);
|
|
ret = 0;
|
|
} else {
|
|
ret = -EAGAIN;
|
|
}
|
|
gru_unlock_gts(gts);
|
|
|
|
gru_dbg(grudev,
|
|
"cb 0x%lx, op %d, exopc %d, cbrstate %d, cbrexecstatus 0x%x, ecause 0x%x, "
|
|
"exdet0 0x%lx, exdet1 0x%x\n",
|
|
excdet.cb, excdet.opc, excdet.exopc, excdet.cbrstate, excdet.cbrexecstatus,
|
|
excdet.ecause, excdet.exceptdet0, excdet.exceptdet1);
|
|
if (!ret && copy_to_user((void __user *)arg, &excdet, sizeof(excdet)))
|
|
ret = -EFAULT;
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* User request to unload a context. Content is saved for possible reload.
|
|
*/
|
|
static int gru_unload_all_contexts(void)
|
|
{
|
|
struct gru_thread_state *gts;
|
|
struct gru_state *gru;
|
|
int gid, ctxnum;
|
|
|
|
if (!capable(CAP_SYS_ADMIN))
|
|
return -EPERM;
|
|
foreach_gid(gid) {
|
|
gru = GID_TO_GRU(gid);
|
|
spin_lock(&gru->gs_lock);
|
|
for (ctxnum = 0; ctxnum < GRU_NUM_CCH; ctxnum++) {
|
|
gts = gru->gs_gts[ctxnum];
|
|
if (gts && mutex_trylock(>s->ts_ctxlock)) {
|
|
spin_unlock(&gru->gs_lock);
|
|
gru_unload_context(gts, 1);
|
|
mutex_unlock(>s->ts_ctxlock);
|
|
spin_lock(&gru->gs_lock);
|
|
}
|
|
}
|
|
spin_unlock(&gru->gs_lock);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int gru_user_unload_context(unsigned long arg)
|
|
{
|
|
struct gru_thread_state *gts;
|
|
struct gru_unload_context_req req;
|
|
|
|
STAT(user_unload_context);
|
|
if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
|
|
return -EFAULT;
|
|
|
|
gru_dbg(grudev, "gseg 0x%lx\n", req.gseg);
|
|
|
|
if (!req.gseg)
|
|
return gru_unload_all_contexts();
|
|
|
|
gts = gru_find_lock_gts(req.gseg);
|
|
if (!gts)
|
|
return -EINVAL;
|
|
|
|
if (gts->ts_gru)
|
|
gru_unload_context(gts, 1);
|
|
gru_unlock_gts(gts);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* User request to flush a range of virtual addresses from the GRU TLB
|
|
* (Mainly for testing).
|
|
*/
|
|
int gru_user_flush_tlb(unsigned long arg)
|
|
{
|
|
struct gru_thread_state *gts;
|
|
struct gru_flush_tlb_req req;
|
|
struct gru_mm_struct *gms;
|
|
|
|
STAT(user_flush_tlb);
|
|
if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
|
|
return -EFAULT;
|
|
|
|
gru_dbg(grudev, "gseg 0x%lx, vaddr 0x%lx, len 0x%lx\n", req.gseg,
|
|
req.vaddr, req.len);
|
|
|
|
gts = gru_find_lock_gts(req.gseg);
|
|
if (!gts)
|
|
return -EINVAL;
|
|
|
|
gms = gts->ts_gms;
|
|
gru_unlock_gts(gts);
|
|
gru_flush_tlb_range(gms, req.vaddr, req.len);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Fetch GSEG statisticss
|
|
*/
|
|
long gru_get_gseg_statistics(unsigned long arg)
|
|
{
|
|
struct gru_thread_state *gts;
|
|
struct gru_get_gseg_statistics_req req;
|
|
|
|
if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
|
|
return -EFAULT;
|
|
|
|
/*
|
|
* The library creates arrays of contexts for threaded programs.
|
|
* If no gts exists in the array, the context has never been used & all
|
|
* statistics are implicitly 0.
|
|
*/
|
|
gts = gru_find_lock_gts(req.gseg);
|
|
if (gts) {
|
|
memcpy(&req.stats, >s->ustats, sizeof(gts->ustats));
|
|
gru_unlock_gts(gts);
|
|
} else {
|
|
memset(&req.stats, 0, sizeof(gts->ustats));
|
|
}
|
|
|
|
if (copy_to_user((void __user *)arg, &req, sizeof(req)))
|
|
return -EFAULT;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Register the current task as the user of the GSEG slice.
|
|
* Needed for TLB fault interrupt targeting.
|
|
*/
|
|
int gru_set_context_option(unsigned long arg)
|
|
{
|
|
struct gru_thread_state *gts;
|
|
struct gru_set_context_option_req req;
|
|
int ret = 0;
|
|
|
|
STAT(set_context_option);
|
|
if (copy_from_user(&req, (void __user *)arg, sizeof(req)))
|
|
return -EFAULT;
|
|
gru_dbg(grudev, "op %d, gseg 0x%lx, value1 0x%lx\n", req.op, req.gseg, req.val1);
|
|
|
|
gts = gru_alloc_locked_gts(req.gseg);
|
|
if (!gts)
|
|
return -EINVAL;
|
|
|
|
switch (req.op) {
|
|
case sco_blade_chiplet:
|
|
/* Select blade/chiplet for GRU context */
|
|
if (req.val1 < -1 || req.val1 >= GRU_MAX_BLADES || !gru_base[req.val1] ||
|
|
req.val0 < -1 || req.val0 >= GRU_CHIPLETS_PER_HUB) {
|
|
ret = -EINVAL;
|
|
} else {
|
|
gts->ts_user_blade_id = req.val1;
|
|
gts->ts_user_chiplet_id = req.val0;
|
|
gru_check_context_placement(gts);
|
|
}
|
|
break;
|
|
case sco_gseg_owner:
|
|
/* Register the current task as the GSEG owner */
|
|
gts->ts_tgid_owner = current->tgid;
|
|
break;
|
|
case sco_cch_req_slice:
|
|
/* Set the CCH slice option */
|
|
gts->ts_cch_req_slice = req.val1 & 3;
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
}
|
|
gru_unlock_gts(gts);
|
|
|
|
return ret;
|
|
}
|