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ac08b1c68d
-----BEGIN PGP SIGNATURE----- iQJIBAABCgAyFiEEgMe7l+5h9hnxdsnuWYigwDrT+vwFAmE3jjYUHGJoZWxnYWFz QGdvb2dsZS5jb20ACgkQWYigwDrT+vwrIA/8DYHYRQ6tR3lY0ZxVeBdnd/ryp/ag z35N8RFLPaFlifLWSldwDV/8dylXnRjS57WS9sppp5gKsLl6xYySvTeMpt5QHdXd gJw27sBqiBmecUGFHWVp9B3yF2LvgrtItjd9RadYaHhWEfWyB5AFK7qwxx02fzvo hoGA2XbpI/Hb1BvSOi1avmPYgly1BRu8RFvKMwB2cxQNv3TZOnekT/iFK5WVR1o2 Z5BA+0nj9PrDO/axS0Vh+TqXhU+hOGox7bkOMcNmbDV7Yo8hgot5SsxddbZqJX+O BNNrRv72pbHGIwT/vOP7OQ49sRXledHYeyEGIixjLylBcROk9t8M1z1sfgJ6obVy 1eM3TIx/+7OS5dxC+gTNMVgUiL1NQIdA1LVIBb0BrXm6yNqNxBlj3o/gQ+VGEiNI 0lATmpe4P/N0/cOSI7tK9O2zsX3qzbLnJxsseGrwtK1L+GRYMUPhP4ciblhB0CIf BmK9j0ROmCBGN0Pz/5wIaQgkTro74dqO1BPX8n84M8KWByNZwTrJo/rCBdD4DGaJ eJvyt3hoYxhSxRQ1rp3zqZ9ytm4dJBGcZBKeO1IvKvJHEzfZBIqqq3M/hlNIaSDP v+8I9HaS1kI4SDB1Ia0LFRqKqvpN+WVLB+EoGkeDQozPO42tYSb43lYe83sEnZ+T KY0a/5feu975eLs= =g1WT -----END PGP SIGNATURE----- Merge tag 'pci-v5.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: "Enumeration: - Convert controller drivers to generic_handle_domain_irq() (Marc Zyngier) - Simplify VPD (Vital Product Data) access and search (Heiner Kallweit) - Update bnx2, bnx2x, bnxt, cxgb4, cxlflash, sfc, tg3 drivers to use simplified VPD interfaces (Heiner Kallweit) - Run Max Payload Size quirks before configuring MPS; work around ASMedia ASM1062 SATA MPS issue (Marek Behún) Resource management: - Refactor pci_ioremap_bar() and pci_ioremap_wc_bar() (Krzysztof Wilczyński) - Optimize pci_resource_len() to reduce kernel size (Zhen Lei) PCI device hotplug: - Fix a double unmap in ibmphp (Vishal Aslot) PCIe port driver: - Enable Bandwidth Notification only if port supports it (Stuart Hayes) Sysfs/proc/syscalls: - Add schedule point in proc_bus_pci_read() (Krzysztof Wilczyński) - Return ~0 data on pciconfig_read() CAP_SYS_ADMIN failure (Krzysztof Wilczyński) - Return "int" from pciconfig_read() syscall (Krzysztof Wilczyński) Virtualization: - Extend "pci=noats" to also turn on Translation Blocking to protect against some DMA attacks (Alex Williamson) - Add sysfs mechanism to control the type of reset used between device assignments to VMs (Amey Narkhede) - Add support for ACPI _RST reset method (Shanker Donthineni) - Add ACS quirks for Cavium multi-function devices (George Cherian) - Add ACS quirks for NXP LX2xx0 and LX2xx2 platforms (Wasim Khan) - Allow HiSilicon AMBA devices that appear as fake PCI devices to use PASID and SVA (Zhangfei Gao) Endpoint framework: - Add support for SR-IOV Endpoint devices (Kishon Vijay Abraham I) - Zero-initialize endpoint test tool parameters so we don't use random parameters (Shunyong Yang) APM X-Gene PCIe controller driver: - Remove redundant dev_err() call in xgene_msi_probe() (ErKun Yang) Broadcom iProc PCIe controller driver: - Don't fail devm_pci_alloc_host_bridge() on missing 'ranges' because it's optional on BCMA devices (Rob Herring) - Fix BCMA probe resource handling (Rob Herring) Cadence PCIe driver: - Work around J7200 Link training electrical issue by increasing delays in LTSSM (Nadeem Athani) Intel IXP4xx PCI controller driver: - Depend on ARCH_IXP4XX to avoid useless config questions (Geert Uytterhoeven) Intel Keembay PCIe controller driver: - Add Intel Keem Bay PCIe controller (Srikanth Thokala) Marvell Aardvark PCIe controller driver: - Work around config space completion handling issues (Evan Wang) - Increase timeout for config access completions (Pali Rohár) - Emulate CRS Software Visibility bit (Pali Rohár) - Configure resources from DT 'ranges' property to fix I/O space access (Pali Rohár) - Serialize INTx mask/unmask (Pali Rohár) MediaTek PCIe controller driver: - Add MT7629 support in DT (Chuanjia Liu) - Fix an MSI issue (Chuanjia Liu) - Get syscon regmap ("mediatek,generic-pciecfg"), IRQ number ("pci_irq"), PCI domain ("linux,pci-domain") from DT properties if present (Chuanjia Liu) Microsoft Hyper-V host bridge driver: - Add ARM64 support (Boqun Feng) - Support "Create Interrupt v3" message (Sunil Muthuswamy) NVIDIA Tegra PCIe controller driver: - Use seq_puts(), move err_msg from stack to static, fix OF node leak (Christophe JAILLET) NVIDIA Tegra194 PCIe driver: - Disable suspend when in Endpoint mode (Om Prakash Singh) - Fix MSI-X address programming error (Om Prakash Singh) - Disable interrupts during suspend to avoid spurious AER link down (Om Prakash Singh) Renesas R-Car PCIe controller driver: - Work around hardware issue that prevents Link L1->L0 transition (Marek Vasut) - Fix runtime PM refcount leak (Dinghao Liu) Rockchip DesignWare PCIe controller driver: - Add Rockchip RK356X host controller driver (Simon Xue) TI J721E PCIe driver: - Add support for J7200 and AM64 (Kishon Vijay Abraham I) Toshiba Visconti PCIe controller driver: - Add Toshiba Visconti PCIe host controller driver (Nobuhiro Iwamatsu) Xilinx NWL PCIe controller driver: - Enable PCIe reference clock via CCF (Hyun Kwon) Miscellaneous: - Convert sta2x11 from 'pci_' to 'dma_' API (Christophe JAILLET) - Fix pci_dev_str_match_path() alloc while atomic bug (used for kernel parameters that specify devices) (Dan Carpenter) - Remove pointless Precision Time Management warning when PTM is present but not enabled (Jakub Kicinski) - Remove surplus "break" statements (Krzysztof Wilczyński)" * tag 'pci-v5.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (132 commits) PCI: ibmphp: Fix double unmap of io_mem x86/PCI: sta2x11: switch from 'pci_' to 'dma_' API PCI/VPD: Use unaligned access helpers PCI/VPD: Clean up public VPD defines and inline functions cxgb4: Use pci_vpd_find_id_string() to find VPD ID string PCI/VPD: Add pci_vpd_find_id_string() PCI/VPD: Include post-processing in pci_vpd_find_tag() PCI/VPD: Stop exporting pci_vpd_find_info_keyword() PCI/VPD: Stop exporting pci_vpd_find_tag() PCI: Set dma-can-stall for HiSilicon chips PCI: rockchip-dwc: Add Rockchip RK356X host controller driver PCI: dwc: Remove surplus break statement after return PCI: artpec6: Remove local code block from switch statement PCI: artpec6: Remove surplus break statement after return MAINTAINERS: Add entries for Toshiba Visconti PCIe controller PCI: visconti: Add Toshiba Visconti PCIe host controller driver PCI/portdrv: Enable Bandwidth Notification only if port supports it PCI: Allow PASID on fake PCIe devices without TLP prefixes PCI: mediatek: Use PCI domain to handle ports detection PCI: mediatek: Add new method to get irq number ...
997 lines
24 KiB
C
997 lines
24 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/**
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* Host side test driver to test endpoint functionality
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*
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* Copyright (C) 2017 Texas Instruments
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*/
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#include <linux/crc32.h>
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#include <linux/delay.h>
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#include <linux/fs.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/miscdevice.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/random.h>
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#include <linux/slab.h>
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#include <linux/uaccess.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/pci_regs.h>
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#include <uapi/linux/pcitest.h>
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#define DRV_MODULE_NAME "pci-endpoint-test"
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#define IRQ_TYPE_UNDEFINED -1
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#define IRQ_TYPE_LEGACY 0
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#define IRQ_TYPE_MSI 1
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#define IRQ_TYPE_MSIX 2
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#define PCI_ENDPOINT_TEST_MAGIC 0x0
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#define PCI_ENDPOINT_TEST_COMMAND 0x4
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#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
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#define COMMAND_RAISE_MSI_IRQ BIT(1)
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#define COMMAND_RAISE_MSIX_IRQ BIT(2)
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#define COMMAND_READ BIT(3)
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#define COMMAND_WRITE BIT(4)
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#define COMMAND_COPY BIT(5)
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#define PCI_ENDPOINT_TEST_STATUS 0x8
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#define STATUS_READ_SUCCESS BIT(0)
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#define STATUS_READ_FAIL BIT(1)
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#define STATUS_WRITE_SUCCESS BIT(2)
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#define STATUS_WRITE_FAIL BIT(3)
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#define STATUS_COPY_SUCCESS BIT(4)
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#define STATUS_COPY_FAIL BIT(5)
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#define STATUS_IRQ_RAISED BIT(6)
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#define STATUS_SRC_ADDR_INVALID BIT(7)
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#define STATUS_DST_ADDR_INVALID BIT(8)
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#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c
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#define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
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#define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
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#define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
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#define PCI_ENDPOINT_TEST_SIZE 0x1c
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#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
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#define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24
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#define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
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#define PCI_ENDPOINT_TEST_FLAGS 0x2c
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#define FLAG_USE_DMA BIT(0)
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#define PCI_DEVICE_ID_TI_AM654 0xb00c
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#define PCI_DEVICE_ID_TI_J7200 0xb00f
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#define PCI_DEVICE_ID_TI_AM64 0xb010
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#define PCI_DEVICE_ID_LS1088A 0x80c0
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#define is_am654_pci_dev(pdev) \
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((pdev)->device == PCI_DEVICE_ID_TI_AM654)
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#define PCI_DEVICE_ID_RENESAS_R8A774A1 0x0028
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#define PCI_DEVICE_ID_RENESAS_R8A774B1 0x002b
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#define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d
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#define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025
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static DEFINE_IDA(pci_endpoint_test_ida);
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#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
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miscdev)
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static bool no_msi;
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module_param(no_msi, bool, 0444);
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MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
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static int irq_type = IRQ_TYPE_MSI;
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module_param(irq_type, int, 0444);
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MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");
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enum pci_barno {
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BAR_0,
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BAR_1,
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BAR_2,
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BAR_3,
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BAR_4,
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BAR_5,
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};
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struct pci_endpoint_test {
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struct pci_dev *pdev;
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void __iomem *base;
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void __iomem *bar[PCI_STD_NUM_BARS];
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struct completion irq_raised;
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int last_irq;
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int num_irqs;
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int irq_type;
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/* mutex to protect the ioctls */
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struct mutex mutex;
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struct miscdevice miscdev;
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enum pci_barno test_reg_bar;
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size_t alignment;
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const char *name;
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};
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struct pci_endpoint_test_data {
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enum pci_barno test_reg_bar;
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size_t alignment;
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int irq_type;
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};
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static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
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u32 offset)
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{
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return readl(test->base + offset);
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}
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static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
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u32 offset, u32 value)
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{
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writel(value, test->base + offset);
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}
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static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
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int bar, int offset)
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{
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return readl(test->bar[bar] + offset);
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}
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static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
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int bar, u32 offset, u32 value)
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{
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writel(value, test->bar[bar] + offset);
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}
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static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
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{
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struct pci_endpoint_test *test = dev_id;
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u32 reg;
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reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
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if (reg & STATUS_IRQ_RAISED) {
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test->last_irq = irq;
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complete(&test->irq_raised);
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reg &= ~STATUS_IRQ_RAISED;
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}
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS,
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reg);
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return IRQ_HANDLED;
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}
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static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test)
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{
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struct pci_dev *pdev = test->pdev;
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pci_free_irq_vectors(pdev);
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test->irq_type = IRQ_TYPE_UNDEFINED;
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}
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static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test,
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int type)
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{
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int irq = -1;
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struct pci_dev *pdev = test->pdev;
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struct device *dev = &pdev->dev;
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bool res = true;
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switch (type) {
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case IRQ_TYPE_LEGACY:
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irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
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if (irq < 0)
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dev_err(dev, "Failed to get Legacy interrupt\n");
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break;
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case IRQ_TYPE_MSI:
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irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
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if (irq < 0)
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dev_err(dev, "Failed to get MSI interrupts\n");
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break;
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case IRQ_TYPE_MSIX:
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irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
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if (irq < 0)
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dev_err(dev, "Failed to get MSI-X interrupts\n");
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break;
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default:
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dev_err(dev, "Invalid IRQ type selected\n");
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}
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if (irq < 0) {
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irq = 0;
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res = false;
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}
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test->irq_type = type;
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test->num_irqs = irq;
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return res;
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}
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static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test)
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{
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int i;
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struct pci_dev *pdev = test->pdev;
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struct device *dev = &pdev->dev;
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for (i = 0; i < test->num_irqs; i++)
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devm_free_irq(dev, pci_irq_vector(pdev, i), test);
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test->num_irqs = 0;
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}
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static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
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{
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int i;
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int err;
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struct pci_dev *pdev = test->pdev;
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struct device *dev = &pdev->dev;
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for (i = 0; i < test->num_irqs; i++) {
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err = devm_request_irq(dev, pci_irq_vector(pdev, i),
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pci_endpoint_test_irqhandler,
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IRQF_SHARED, test->name, test);
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if (err)
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goto fail;
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}
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return true;
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fail:
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switch (irq_type) {
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case IRQ_TYPE_LEGACY:
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dev_err(dev, "Failed to request IRQ %d for Legacy\n",
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pci_irq_vector(pdev, i));
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break;
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case IRQ_TYPE_MSI:
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dev_err(dev, "Failed to request IRQ %d for MSI %d\n",
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pci_irq_vector(pdev, i),
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i + 1);
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break;
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case IRQ_TYPE_MSIX:
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dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n",
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pci_irq_vector(pdev, i),
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i + 1);
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break;
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}
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return false;
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}
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static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
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enum pci_barno barno)
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{
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int j;
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u32 val;
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int size;
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struct pci_dev *pdev = test->pdev;
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if (!test->bar[barno])
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return false;
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size = pci_resource_len(pdev, barno);
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if (barno == test->test_reg_bar)
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size = 0x4;
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for (j = 0; j < size; j += 4)
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pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
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for (j = 0; j < size; j += 4) {
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val = pci_endpoint_test_bar_readl(test, barno, j);
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if (val != 0xA0A0A0A0)
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return false;
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}
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return true;
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}
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static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
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{
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u32 val;
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
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IRQ_TYPE_LEGACY);
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
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COMMAND_RAISE_LEGACY_IRQ);
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val = wait_for_completion_timeout(&test->irq_raised,
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msecs_to_jiffies(1000));
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if (!val)
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return false;
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return true;
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}
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static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
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u16 msi_num, bool msix)
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{
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u32 val;
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struct pci_dev *pdev = test->pdev;
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
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msix == false ? IRQ_TYPE_MSI :
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IRQ_TYPE_MSIX);
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num);
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pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
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msix == false ? COMMAND_RAISE_MSI_IRQ :
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COMMAND_RAISE_MSIX_IRQ);
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val = wait_for_completion_timeout(&test->irq_raised,
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msecs_to_jiffies(1000));
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if (!val)
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return false;
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if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq)
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return true;
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return false;
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}
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static bool pci_endpoint_test_copy(struct pci_endpoint_test *test,
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unsigned long arg)
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{
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struct pci_endpoint_test_xfer_param param;
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bool ret = false;
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void *src_addr;
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void *dst_addr;
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u32 flags = 0;
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bool use_dma;
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size_t size;
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dma_addr_t src_phys_addr;
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dma_addr_t dst_phys_addr;
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struct pci_dev *pdev = test->pdev;
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struct device *dev = &pdev->dev;
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void *orig_src_addr;
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dma_addr_t orig_src_phys_addr;
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void *orig_dst_addr;
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dma_addr_t orig_dst_phys_addr;
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size_t offset;
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size_t alignment = test->alignment;
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int irq_type = test->irq_type;
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u32 src_crc32;
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u32 dst_crc32;
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int err;
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err = copy_from_user(¶m, (void __user *)arg, sizeof(param));
|
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if (err) {
|
|
dev_err(dev, "Failed to get transfer param\n");
|
|
return false;
|
|
}
|
|
|
|
size = param.size;
|
|
if (size > SIZE_MAX - alignment)
|
|
goto err;
|
|
|
|
use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
|
|
if (use_dma)
|
|
flags |= FLAG_USE_DMA;
|
|
|
|
if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
|
|
dev_err(dev, "Invalid IRQ type option\n");
|
|
goto err;
|
|
}
|
|
|
|
orig_src_addr = kzalloc(size + alignment, GFP_KERNEL);
|
|
if (!orig_src_addr) {
|
|
dev_err(dev, "Failed to allocate source buffer\n");
|
|
ret = false;
|
|
goto err;
|
|
}
|
|
|
|
get_random_bytes(orig_src_addr, size + alignment);
|
|
orig_src_phys_addr = dma_map_single(dev, orig_src_addr,
|
|
size + alignment, DMA_TO_DEVICE);
|
|
if (dma_mapping_error(dev, orig_src_phys_addr)) {
|
|
dev_err(dev, "failed to map source buffer address\n");
|
|
ret = false;
|
|
goto err_src_phys_addr;
|
|
}
|
|
|
|
if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) {
|
|
src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment);
|
|
offset = src_phys_addr - orig_src_phys_addr;
|
|
src_addr = orig_src_addr + offset;
|
|
} else {
|
|
src_phys_addr = orig_src_phys_addr;
|
|
src_addr = orig_src_addr;
|
|
}
|
|
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
|
|
lower_32_bits(src_phys_addr));
|
|
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
|
|
upper_32_bits(src_phys_addr));
|
|
|
|
src_crc32 = crc32_le(~0, src_addr, size);
|
|
|
|
orig_dst_addr = kzalloc(size + alignment, GFP_KERNEL);
|
|
if (!orig_dst_addr) {
|
|
dev_err(dev, "Failed to allocate destination address\n");
|
|
ret = false;
|
|
goto err_dst_addr;
|
|
}
|
|
|
|
orig_dst_phys_addr = dma_map_single(dev, orig_dst_addr,
|
|
size + alignment, DMA_FROM_DEVICE);
|
|
if (dma_mapping_error(dev, orig_dst_phys_addr)) {
|
|
dev_err(dev, "failed to map destination buffer address\n");
|
|
ret = false;
|
|
goto err_dst_phys_addr;
|
|
}
|
|
|
|
if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) {
|
|
dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment);
|
|
offset = dst_phys_addr - orig_dst_phys_addr;
|
|
dst_addr = orig_dst_addr + offset;
|
|
} else {
|
|
dst_phys_addr = orig_dst_phys_addr;
|
|
dst_addr = orig_dst_addr;
|
|
}
|
|
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
|
|
lower_32_bits(dst_phys_addr));
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
|
|
upper_32_bits(dst_phys_addr));
|
|
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
|
|
size);
|
|
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
|
|
COMMAND_COPY);
|
|
|
|
wait_for_completion(&test->irq_raised);
|
|
|
|
dma_unmap_single(dev, orig_dst_phys_addr, size + alignment,
|
|
DMA_FROM_DEVICE);
|
|
|
|
dst_crc32 = crc32_le(~0, dst_addr, size);
|
|
if (dst_crc32 == src_crc32)
|
|
ret = true;
|
|
|
|
err_dst_phys_addr:
|
|
kfree(orig_dst_addr);
|
|
|
|
err_dst_addr:
|
|
dma_unmap_single(dev, orig_src_phys_addr, size + alignment,
|
|
DMA_TO_DEVICE);
|
|
|
|
err_src_phys_addr:
|
|
kfree(orig_src_addr);
|
|
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
static bool pci_endpoint_test_write(struct pci_endpoint_test *test,
|
|
unsigned long arg)
|
|
{
|
|
struct pci_endpoint_test_xfer_param param;
|
|
bool ret = false;
|
|
u32 flags = 0;
|
|
bool use_dma;
|
|
u32 reg;
|
|
void *addr;
|
|
dma_addr_t phys_addr;
|
|
struct pci_dev *pdev = test->pdev;
|
|
struct device *dev = &pdev->dev;
|
|
void *orig_addr;
|
|
dma_addr_t orig_phys_addr;
|
|
size_t offset;
|
|
size_t alignment = test->alignment;
|
|
int irq_type = test->irq_type;
|
|
size_t size;
|
|
u32 crc32;
|
|
int err;
|
|
|
|
err = copy_from_user(¶m, (void __user *)arg, sizeof(param));
|
|
if (err != 0) {
|
|
dev_err(dev, "Failed to get transfer param\n");
|
|
return false;
|
|
}
|
|
|
|
size = param.size;
|
|
if (size > SIZE_MAX - alignment)
|
|
goto err;
|
|
|
|
use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
|
|
if (use_dma)
|
|
flags |= FLAG_USE_DMA;
|
|
|
|
if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
|
|
dev_err(dev, "Invalid IRQ type option\n");
|
|
goto err;
|
|
}
|
|
|
|
orig_addr = kzalloc(size + alignment, GFP_KERNEL);
|
|
if (!orig_addr) {
|
|
dev_err(dev, "Failed to allocate address\n");
|
|
ret = false;
|
|
goto err;
|
|
}
|
|
|
|
get_random_bytes(orig_addr, size + alignment);
|
|
|
|
orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment,
|
|
DMA_TO_DEVICE);
|
|
if (dma_mapping_error(dev, orig_phys_addr)) {
|
|
dev_err(dev, "failed to map source buffer address\n");
|
|
ret = false;
|
|
goto err_phys_addr;
|
|
}
|
|
|
|
if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
|
|
phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
|
|
offset = phys_addr - orig_phys_addr;
|
|
addr = orig_addr + offset;
|
|
} else {
|
|
phys_addr = orig_phys_addr;
|
|
addr = orig_addr;
|
|
}
|
|
|
|
crc32 = crc32_le(~0, addr, size);
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
|
|
crc32);
|
|
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
|
|
lower_32_bits(phys_addr));
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
|
|
upper_32_bits(phys_addr));
|
|
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
|
|
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
|
|
COMMAND_READ);
|
|
|
|
wait_for_completion(&test->irq_raised);
|
|
|
|
reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
|
|
if (reg & STATUS_READ_SUCCESS)
|
|
ret = true;
|
|
|
|
dma_unmap_single(dev, orig_phys_addr, size + alignment,
|
|
DMA_TO_DEVICE);
|
|
|
|
err_phys_addr:
|
|
kfree(orig_addr);
|
|
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
static bool pci_endpoint_test_read(struct pci_endpoint_test *test,
|
|
unsigned long arg)
|
|
{
|
|
struct pci_endpoint_test_xfer_param param;
|
|
bool ret = false;
|
|
u32 flags = 0;
|
|
bool use_dma;
|
|
size_t size;
|
|
void *addr;
|
|
dma_addr_t phys_addr;
|
|
struct pci_dev *pdev = test->pdev;
|
|
struct device *dev = &pdev->dev;
|
|
void *orig_addr;
|
|
dma_addr_t orig_phys_addr;
|
|
size_t offset;
|
|
size_t alignment = test->alignment;
|
|
int irq_type = test->irq_type;
|
|
u32 crc32;
|
|
int err;
|
|
|
|
err = copy_from_user(¶m, (void __user *)arg, sizeof(param));
|
|
if (err) {
|
|
dev_err(dev, "Failed to get transfer param\n");
|
|
return false;
|
|
}
|
|
|
|
size = param.size;
|
|
if (size > SIZE_MAX - alignment)
|
|
goto err;
|
|
|
|
use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
|
|
if (use_dma)
|
|
flags |= FLAG_USE_DMA;
|
|
|
|
if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
|
|
dev_err(dev, "Invalid IRQ type option\n");
|
|
goto err;
|
|
}
|
|
|
|
orig_addr = kzalloc(size + alignment, GFP_KERNEL);
|
|
if (!orig_addr) {
|
|
dev_err(dev, "Failed to allocate destination address\n");
|
|
ret = false;
|
|
goto err;
|
|
}
|
|
|
|
orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment,
|
|
DMA_FROM_DEVICE);
|
|
if (dma_mapping_error(dev, orig_phys_addr)) {
|
|
dev_err(dev, "failed to map source buffer address\n");
|
|
ret = false;
|
|
goto err_phys_addr;
|
|
}
|
|
|
|
if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
|
|
phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
|
|
offset = phys_addr - orig_phys_addr;
|
|
addr = orig_addr + offset;
|
|
} else {
|
|
phys_addr = orig_phys_addr;
|
|
addr = orig_addr;
|
|
}
|
|
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
|
|
lower_32_bits(phys_addr));
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
|
|
upper_32_bits(phys_addr));
|
|
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
|
|
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
|
|
pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
|
|
COMMAND_WRITE);
|
|
|
|
wait_for_completion(&test->irq_raised);
|
|
|
|
dma_unmap_single(dev, orig_phys_addr, size + alignment,
|
|
DMA_FROM_DEVICE);
|
|
|
|
crc32 = crc32_le(~0, addr, size);
|
|
if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
|
|
ret = true;
|
|
|
|
err_phys_addr:
|
|
kfree(orig_addr);
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
static bool pci_endpoint_test_clear_irq(struct pci_endpoint_test *test)
|
|
{
|
|
pci_endpoint_test_release_irq(test);
|
|
pci_endpoint_test_free_irq_vectors(test);
|
|
return true;
|
|
}
|
|
|
|
static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test,
|
|
int req_irq_type)
|
|
{
|
|
struct pci_dev *pdev = test->pdev;
|
|
struct device *dev = &pdev->dev;
|
|
|
|
if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) {
|
|
dev_err(dev, "Invalid IRQ type option\n");
|
|
return false;
|
|
}
|
|
|
|
if (test->irq_type == req_irq_type)
|
|
return true;
|
|
|
|
pci_endpoint_test_release_irq(test);
|
|
pci_endpoint_test_free_irq_vectors(test);
|
|
|
|
if (!pci_endpoint_test_alloc_irq_vectors(test, req_irq_type))
|
|
goto err;
|
|
|
|
if (!pci_endpoint_test_request_irq(test))
|
|
goto err;
|
|
|
|
return true;
|
|
|
|
err:
|
|
pci_endpoint_test_free_irq_vectors(test);
|
|
return false;
|
|
}
|
|
|
|
static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
|
|
unsigned long arg)
|
|
{
|
|
int ret = -EINVAL;
|
|
enum pci_barno bar;
|
|
struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
|
|
struct pci_dev *pdev = test->pdev;
|
|
|
|
mutex_lock(&test->mutex);
|
|
switch (cmd) {
|
|
case PCITEST_BAR:
|
|
bar = arg;
|
|
if (bar > BAR_5)
|
|
goto ret;
|
|
if (is_am654_pci_dev(pdev) && bar == BAR_0)
|
|
goto ret;
|
|
ret = pci_endpoint_test_bar(test, bar);
|
|
break;
|
|
case PCITEST_LEGACY_IRQ:
|
|
ret = pci_endpoint_test_legacy_irq(test);
|
|
break;
|
|
case PCITEST_MSI:
|
|
case PCITEST_MSIX:
|
|
ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX);
|
|
break;
|
|
case PCITEST_WRITE:
|
|
ret = pci_endpoint_test_write(test, arg);
|
|
break;
|
|
case PCITEST_READ:
|
|
ret = pci_endpoint_test_read(test, arg);
|
|
break;
|
|
case PCITEST_COPY:
|
|
ret = pci_endpoint_test_copy(test, arg);
|
|
break;
|
|
case PCITEST_SET_IRQTYPE:
|
|
ret = pci_endpoint_test_set_irq(test, arg);
|
|
break;
|
|
case PCITEST_GET_IRQTYPE:
|
|
ret = irq_type;
|
|
break;
|
|
case PCITEST_CLEAR_IRQ:
|
|
ret = pci_endpoint_test_clear_irq(test);
|
|
break;
|
|
}
|
|
|
|
ret:
|
|
mutex_unlock(&test->mutex);
|
|
return ret;
|
|
}
|
|
|
|
static const struct file_operations pci_endpoint_test_fops = {
|
|
.owner = THIS_MODULE,
|
|
.unlocked_ioctl = pci_endpoint_test_ioctl,
|
|
};
|
|
|
|
static int pci_endpoint_test_probe(struct pci_dev *pdev,
|
|
const struct pci_device_id *ent)
|
|
{
|
|
int err;
|
|
int id;
|
|
char name[24];
|
|
enum pci_barno bar;
|
|
void __iomem *base;
|
|
struct device *dev = &pdev->dev;
|
|
struct pci_endpoint_test *test;
|
|
struct pci_endpoint_test_data *data;
|
|
enum pci_barno test_reg_bar = BAR_0;
|
|
struct miscdevice *misc_device;
|
|
|
|
if (pci_is_bridge(pdev))
|
|
return -ENODEV;
|
|
|
|
test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
|
|
if (!test)
|
|
return -ENOMEM;
|
|
|
|
test->test_reg_bar = 0;
|
|
test->alignment = 0;
|
|
test->pdev = pdev;
|
|
test->irq_type = IRQ_TYPE_UNDEFINED;
|
|
|
|
if (no_msi)
|
|
irq_type = IRQ_TYPE_LEGACY;
|
|
|
|
data = (struct pci_endpoint_test_data *)ent->driver_data;
|
|
if (data) {
|
|
test_reg_bar = data->test_reg_bar;
|
|
test->test_reg_bar = test_reg_bar;
|
|
test->alignment = data->alignment;
|
|
irq_type = data->irq_type;
|
|
}
|
|
|
|
init_completion(&test->irq_raised);
|
|
mutex_init(&test->mutex);
|
|
|
|
if ((dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48)) != 0) &&
|
|
dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
|
|
dev_err(dev, "Cannot set DMA mask\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
err = pci_enable_device(pdev);
|
|
if (err) {
|
|
dev_err(dev, "Cannot enable PCI device\n");
|
|
return err;
|
|
}
|
|
|
|
err = pci_request_regions(pdev, DRV_MODULE_NAME);
|
|
if (err) {
|
|
dev_err(dev, "Cannot obtain PCI resources\n");
|
|
goto err_disable_pdev;
|
|
}
|
|
|
|
pci_set_master(pdev);
|
|
|
|
if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type)) {
|
|
err = -EINVAL;
|
|
goto err_disable_irq;
|
|
}
|
|
|
|
for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
|
|
if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
|
|
base = pci_ioremap_bar(pdev, bar);
|
|
if (!base) {
|
|
dev_err(dev, "Failed to read BAR%d\n", bar);
|
|
WARN_ON(bar == test_reg_bar);
|
|
}
|
|
test->bar[bar] = base;
|
|
}
|
|
}
|
|
|
|
test->base = test->bar[test_reg_bar];
|
|
if (!test->base) {
|
|
err = -ENOMEM;
|
|
dev_err(dev, "Cannot perform PCI test without BAR%d\n",
|
|
test_reg_bar);
|
|
goto err_iounmap;
|
|
}
|
|
|
|
pci_set_drvdata(pdev, test);
|
|
|
|
id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
|
|
if (id < 0) {
|
|
err = id;
|
|
dev_err(dev, "Unable to get id\n");
|
|
goto err_iounmap;
|
|
}
|
|
|
|
snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
|
|
test->name = kstrdup(name, GFP_KERNEL);
|
|
if (!test->name) {
|
|
err = -ENOMEM;
|
|
goto err_ida_remove;
|
|
}
|
|
|
|
if (!pci_endpoint_test_request_irq(test)) {
|
|
err = -EINVAL;
|
|
goto err_kfree_test_name;
|
|
}
|
|
|
|
misc_device = &test->miscdev;
|
|
misc_device->minor = MISC_DYNAMIC_MINOR;
|
|
misc_device->name = kstrdup(name, GFP_KERNEL);
|
|
if (!misc_device->name) {
|
|
err = -ENOMEM;
|
|
goto err_release_irq;
|
|
}
|
|
misc_device->parent = &pdev->dev;
|
|
misc_device->fops = &pci_endpoint_test_fops,
|
|
|
|
err = misc_register(misc_device);
|
|
if (err) {
|
|
dev_err(dev, "Failed to register device\n");
|
|
goto err_kfree_name;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_kfree_name:
|
|
kfree(misc_device->name);
|
|
|
|
err_release_irq:
|
|
pci_endpoint_test_release_irq(test);
|
|
|
|
err_kfree_test_name:
|
|
kfree(test->name);
|
|
|
|
err_ida_remove:
|
|
ida_simple_remove(&pci_endpoint_test_ida, id);
|
|
|
|
err_iounmap:
|
|
for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
|
|
if (test->bar[bar])
|
|
pci_iounmap(pdev, test->bar[bar]);
|
|
}
|
|
|
|
err_disable_irq:
|
|
pci_endpoint_test_free_irq_vectors(test);
|
|
pci_release_regions(pdev);
|
|
|
|
err_disable_pdev:
|
|
pci_disable_device(pdev);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void pci_endpoint_test_remove(struct pci_dev *pdev)
|
|
{
|
|
int id;
|
|
enum pci_barno bar;
|
|
struct pci_endpoint_test *test = pci_get_drvdata(pdev);
|
|
struct miscdevice *misc_device = &test->miscdev;
|
|
|
|
if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
|
|
return;
|
|
if (id < 0)
|
|
return;
|
|
|
|
misc_deregister(&test->miscdev);
|
|
kfree(misc_device->name);
|
|
kfree(test->name);
|
|
ida_simple_remove(&pci_endpoint_test_ida, id);
|
|
for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
|
|
if (test->bar[bar])
|
|
pci_iounmap(pdev, test->bar[bar]);
|
|
}
|
|
|
|
pci_endpoint_test_release_irq(test);
|
|
pci_endpoint_test_free_irq_vectors(test);
|
|
|
|
pci_release_regions(pdev);
|
|
pci_disable_device(pdev);
|
|
}
|
|
|
|
static const struct pci_endpoint_test_data default_data = {
|
|
.test_reg_bar = BAR_0,
|
|
.alignment = SZ_4K,
|
|
.irq_type = IRQ_TYPE_MSI,
|
|
};
|
|
|
|
static const struct pci_endpoint_test_data am654_data = {
|
|
.test_reg_bar = BAR_2,
|
|
.alignment = SZ_64K,
|
|
.irq_type = IRQ_TYPE_MSI,
|
|
};
|
|
|
|
static const struct pci_endpoint_test_data j721e_data = {
|
|
.alignment = 256,
|
|
.irq_type = IRQ_TYPE_MSI,
|
|
};
|
|
|
|
static const struct pci_device_id pci_endpoint_test_tbl[] = {
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x),
|
|
.driver_data = (kernel_ulong_t)&default_data,
|
|
},
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x),
|
|
.driver_data = (kernel_ulong_t)&default_data,
|
|
},
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0),
|
|
.driver_data = (kernel_ulong_t)&default_data,
|
|
},
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_LS1088A),
|
|
.driver_data = (kernel_ulong_t)&default_data,
|
|
},
|
|
{ PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
|
|
.driver_data = (kernel_ulong_t)&am654_data
|
|
},
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774A1),},
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),},
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),},
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774E1),},
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),
|
|
.driver_data = (kernel_ulong_t)&j721e_data,
|
|
},
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J7200),
|
|
.driver_data = (kernel_ulong_t)&j721e_data,
|
|
},
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM64),
|
|
.driver_data = (kernel_ulong_t)&j721e_data,
|
|
},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
|
|
|
|
static struct pci_driver pci_endpoint_test_driver = {
|
|
.name = DRV_MODULE_NAME,
|
|
.id_table = pci_endpoint_test_tbl,
|
|
.probe = pci_endpoint_test_probe,
|
|
.remove = pci_endpoint_test_remove,
|
|
.sriov_configure = pci_sriov_configure_simple,
|
|
};
|
|
module_pci_driver(pci_endpoint_test_driver);
|
|
|
|
MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
|
|
MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
|
|
MODULE_LICENSE("GPL v2");
|