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4e562c1166
There are two generations of tlb operation instruction for C-SKY. First generation is use mcr register and it need software do more things, second generation is use specific instructions, eg: tlbi.va, tlbi.vas, tlbi.alls We implemented the following functions: - flush_tlb_range (a range of entries) - flush_tlb_page (one entry) Above functions use asid from vma->mm to invalid tlb entries and we could use tlbi.vas instruction for newest generation csky cpu. - flush_tlb_kernel_range - flush_tlb_one Above functions don't care asid and it invalid the tlb entries only with vpn and we could use tlbi.vaas instruction for newest generat- ion csky cpu. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de>
172 lines
3.3 KiB
C
172 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/setup.h>
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/*
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* One C-SKY MMU TLB entry contain two PFN/page entry, ie:
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* 1VPN -> 2PFN
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*/
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#define TLB_ENTRY_SIZE (PAGE_SIZE * 2)
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#define TLB_ENTRY_SIZE_MASK (PAGE_MASK << 1)
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void flush_tlb_all(void)
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{
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tlb_invalid_all();
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}
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void flush_tlb_mm(struct mm_struct *mm)
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{
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#ifdef CONFIG_CPU_HAS_TLBI
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asm volatile("tlbi.asids %0"::"r"(cpu_asid(mm)));
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#else
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tlb_invalid_all();
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#endif
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}
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/*
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* MMU operation regs only could invalid tlb entry in jtlb and we
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* need change asid field to invalid I-utlb & D-utlb.
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*/
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#ifndef CONFIG_CPU_HAS_TLBI
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#define restore_asid_inv_utlb(oldpid, newpid) \
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do { \
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if (oldpid == newpid) \
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write_mmu_entryhi(oldpid + 1); \
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write_mmu_entryhi(oldpid); \
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} while (0)
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#endif
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void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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unsigned long newpid = cpu_asid(vma->vm_mm);
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start &= TLB_ENTRY_SIZE_MASK;
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end += TLB_ENTRY_SIZE - 1;
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end &= TLB_ENTRY_SIZE_MASK;
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#ifdef CONFIG_CPU_HAS_TLBI
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while (start < end) {
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asm volatile("tlbi.vas %0"::"r"(start | newpid));
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start += 2*PAGE_SIZE;
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}
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sync_is();
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#else
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{
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unsigned long flags, oldpid;
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local_irq_save(flags);
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oldpid = read_mmu_entryhi() & ASID_MASK;
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while (start < end) {
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int idx;
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write_mmu_entryhi(start | newpid);
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start += 2*PAGE_SIZE;
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tlb_probe();
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idx = read_mmu_index();
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if (idx >= 0)
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tlb_invalid_indexed();
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}
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restore_asid_inv_utlb(oldpid, newpid);
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local_irq_restore(flags);
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}
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#endif
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}
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void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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start &= TLB_ENTRY_SIZE_MASK;
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end += TLB_ENTRY_SIZE - 1;
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end &= TLB_ENTRY_SIZE_MASK;
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#ifdef CONFIG_CPU_HAS_TLBI
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while (start < end) {
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asm volatile("tlbi.vaas %0"::"r"(start));
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start += 2*PAGE_SIZE;
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}
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sync_is();
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#else
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{
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unsigned long flags, oldpid;
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local_irq_save(flags);
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oldpid = read_mmu_entryhi() & ASID_MASK;
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while (start < end) {
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int idx;
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write_mmu_entryhi(start | oldpid);
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start += 2*PAGE_SIZE;
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tlb_probe();
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idx = read_mmu_index();
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if (idx >= 0)
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tlb_invalid_indexed();
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}
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restore_asid_inv_utlb(oldpid, oldpid);
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local_irq_restore(flags);
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}
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#endif
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}
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
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{
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int newpid = cpu_asid(vma->vm_mm);
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addr &= TLB_ENTRY_SIZE_MASK;
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#ifdef CONFIG_CPU_HAS_TLBI
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asm volatile("tlbi.vas %0"::"r"(addr | newpid));
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sync_is();
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#else
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{
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int oldpid, idx;
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unsigned long flags;
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local_irq_save(flags);
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oldpid = read_mmu_entryhi() & ASID_MASK;
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write_mmu_entryhi(addr | newpid);
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tlb_probe();
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idx = read_mmu_index();
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if (idx >= 0)
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tlb_invalid_indexed();
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restore_asid_inv_utlb(oldpid, newpid);
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local_irq_restore(flags);
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}
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#endif
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}
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void flush_tlb_one(unsigned long addr)
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{
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addr &= TLB_ENTRY_SIZE_MASK;
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#ifdef CONFIG_CPU_HAS_TLBI
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asm volatile("tlbi.vaas %0"::"r"(addr));
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sync_is();
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#else
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{
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int oldpid, idx;
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unsigned long flags;
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local_irq_save(flags);
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oldpid = read_mmu_entryhi() & ASID_MASK;
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write_mmu_entryhi(addr | oldpid);
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tlb_probe();
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idx = read_mmu_index();
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if (idx >= 0)
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tlb_invalid_indexed();
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restore_asid_inv_utlb(oldpid, oldpid);
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local_irq_restore(flags);
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}
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#endif
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}
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EXPORT_SYMBOL(flush_tlb_one);
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