Peter Zijlstra 991625f3dd x86/ibt: Add IBT feature, MSR and #CP handling ... The bits required to make the hardware go.. Of note is that, provided the syscall entry points are covered with ENDBR, #CP doesn't need to be an IST because we'll never hit the syscall gap. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Josh Poimboeuf <jpoimboe@redhat.com> Link: https://lore.kernel.org/r/20220308154318.582331711@infradead.org		2022-03-15 10:32:39 +01:00
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asm	x86/ibt: Add IBT feature, MSR and #CP handling	2022-03-15 10:32:39 +01:00
uapi/asm	x86/ibt: Add IBT feature, MSR and #CP handling	2022-03-15 10:32:39 +01:00