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8d60a903d9
This patch explicitly removes the kgdb implementation, for mips which is intended to be followed by a patch that adds a kgdb implementation for MIPS that makes use of the kgdb core in the kernel. Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
238 lines
6.5 KiB
C
238 lines
6.5 KiB
C
/*
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*
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* Copyright (C) 2005 Embedded Alley Solutions, Inc
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* Ported to 2.6.
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*
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* Per Hallsmark, per.hallsmark@mvista.com
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* Copyright (C) 2000, 2001 MIPS Technologies, Inc.
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* Copyright (C) 2001 Ralf Baechle
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*
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* Cleaned up and bug fixing: Pete Popov, ppopov@embeddedalley.com
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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*/
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#include <linux/compiler.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/random.h>
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#include <linux/module.h>
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#include <asm/io.h>
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#include <int.h>
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#include <uart.h>
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/* default prio for interrupts */
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/* first one is a no-no so therefore always prio 0 (disabled) */
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static char gic_prio[PNX8550_INT_GIC_TOTINT] = {
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0, 1, 1, 1, 1, 15, 1, 1, 1, 1, // 0 - 9
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 10 - 19
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 20 - 29
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 30 - 39
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 40 - 49
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1, 1, 1, 1, 1, 1, 1, 1, 2, 1, // 50 - 59
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1, 1, 1, 1, 1, 1, 1, 1, 1, 1, // 60 - 69
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1 // 70
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};
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static void hw0_irqdispatch(int irq)
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{
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/* find out which interrupt */
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irq = PNX8550_GIC_VECTOR_0 >> 3;
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if (irq == 0) {
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printk("hw0_irqdispatch: irq 0, spurious interrupt?\n");
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return;
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}
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do_IRQ(PNX8550_INT_GIC_MIN + irq);
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}
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static void timer_irqdispatch(int irq)
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{
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irq = (0x01c0 & read_c0_config7()) >> 6;
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if (unlikely(irq == 0)) {
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printk("timer_irqdispatch: irq 0, spurious interrupt?\n");
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return;
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}
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if (irq & 0x1)
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do_IRQ(PNX8550_INT_TIMER1);
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if (irq & 0x2)
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do_IRQ(PNX8550_INT_TIMER2);
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if (irq & 0x4)
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do_IRQ(PNX8550_INT_TIMER3);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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if (pending & STATUSF_IP2)
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hw0_irqdispatch(2);
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else if (pending & STATUSF_IP7) {
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if (read_c0_config7() & 0x01c0)
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timer_irqdispatch(7);
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} else
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spurious_interrupt();
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}
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static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask)
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{
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unsigned long status = read_c0_status();
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status &= ~((clr_mask & 0xFF) << 8);
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status |= (set_mask & 0xFF) << 8;
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write_c0_status(status);
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}
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static inline void mask_gic_int(unsigned int irq_nr)
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{
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/* interrupt disabled, bit 26(WE_ENABLE)=1 and bit 16(enable)=0 */
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PNX8550_GIC_REQ(irq_nr) = 1<<28; /* set priority to 0 */
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}
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static inline void unmask_gic_int(unsigned int irq_nr)
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{
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/* set prio mask to lower four bits and enable interrupt */
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PNX8550_GIC_REQ(irq_nr) = (1<<26 | 1<<16) | (1<<28) | gic_prio[irq_nr];
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}
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static inline void mask_irq(unsigned int irq_nr)
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{
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if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
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modify_cp0_intmask(1 << irq_nr, 0);
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} else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
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(irq_nr <= PNX8550_INT_GIC_MAX)) {
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mask_gic_int(irq_nr - PNX8550_INT_GIC_MIN);
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} else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
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(irq_nr <= PNX8550_INT_TIMER_MAX)) {
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modify_cp0_intmask(1 << 7, 0);
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} else {
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printk("mask_irq: irq %d doesn't exist!\n", irq_nr);
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}
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}
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static inline void unmask_irq(unsigned int irq_nr)
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{
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if ((PNX8550_INT_CP0_MIN <= irq_nr) && (irq_nr <= PNX8550_INT_CP0_MAX)) {
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modify_cp0_intmask(0, 1 << irq_nr);
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} else if ((PNX8550_INT_GIC_MIN <= irq_nr) &&
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(irq_nr <= PNX8550_INT_GIC_MAX)) {
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unmask_gic_int(irq_nr - PNX8550_INT_GIC_MIN);
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} else if ((PNX8550_INT_TIMER_MIN <= irq_nr) &&
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(irq_nr <= PNX8550_INT_TIMER_MAX)) {
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modify_cp0_intmask(0, 1 << 7);
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} else {
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printk("mask_irq: irq %d doesn't exist!\n", irq_nr);
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}
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}
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int pnx8550_set_gic_priority(int irq, int priority)
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{
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int gic_irq = irq-PNX8550_INT_GIC_MIN;
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int prev_priority = PNX8550_GIC_REQ(gic_irq) & 0xf;
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gic_prio[gic_irq] = priority;
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PNX8550_GIC_REQ(gic_irq) |= (0x10000000 | gic_prio[gic_irq]);
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return prev_priority;
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}
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static struct irq_chip level_irq_type = {
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.name = "PNX Level IRQ",
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.ack = mask_irq,
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.mask = mask_irq,
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.mask_ack = mask_irq,
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.unmask = unmask_irq,
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};
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static struct irqaction gic_action = {
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.handler = no_action,
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.flags = IRQF_DISABLED,
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.name = "GIC",
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};
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static struct irqaction timer_action = {
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.handler = no_action,
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.flags = IRQF_DISABLED,
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.name = "Timer",
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};
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void __init arch_init_irq(void)
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{
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int i;
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int configPR;
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for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
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set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
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mask_irq(i); /* mask the irq just in case */
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}
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/* init of GIC/IPC interrupts */
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/* should be done before cp0 since cp0 init enables the GIC int */
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for (i = PNX8550_INT_GIC_MIN; i <= PNX8550_INT_GIC_MAX; i++) {
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int gic_int_line = i - PNX8550_INT_GIC_MIN;
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if (gic_int_line == 0 )
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continue; // don't fiddle with int 0
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/*
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* enable change of TARGET, ENABLE and ACTIVE_LOW bits
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* set TARGET 0 to route through hw0 interrupt
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* set ACTIVE_LOW 0 active high (correct?)
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*
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* We really should setup an interrupt description table
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* to do this nicely.
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* Note, PCI INTA is active low on the bus, but inverted
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* in the GIC, so to us it's active high.
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*/
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PNX8550_GIC_REQ(i - PNX8550_INT_GIC_MIN) = 0x1E000000;
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/* mask/priority is still 0 so we will not get any
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* interrupts until it is unmasked */
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set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
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}
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/* Priority level 0 */
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PNX8550_GIC_PRIMASK_0 = PNX8550_GIC_PRIMASK_1 = 0;
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/* Set int vector table address */
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PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
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set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type,
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handle_level_irq);
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setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
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/* init of Timer interrupts */
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for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++)
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set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
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/* Stop Timer 1-3 */
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configPR = read_c0_config7();
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configPR |= 0x00000038;
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write_c0_config7(configPR);
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set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type,
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handle_level_irq);
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setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
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}
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EXPORT_SYMBOL(pnx8550_set_gic_priority);
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