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b828f96021
The L2C-220 (AKA L220) and L2C-310 (AKA PL310) cache controllers feature a Performance Monitoring Unit (PMU), which can be useful for tuning and/or debugging. This hardware is always present and the relevant registers are accessible to non-secure accesses. Thus, no special firmware interface is necessary. This patch adds support for the PMU, plugging into the usual perf infrastructure. The overflow interrupt is not always available (e.g. on RealView PBX A9 it is not wired up at all), and the hardware counters saturate, so the driver does not make use of this. Instead, the driver periodically polls and reset counters as required to avoid losing events due to saturation. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Pawel Moll <pawel.moll@arm.com> Tested-by: Kim Phillips <kim.phillips@arm.com> Cc: Russell King <linux@armlinux.org.uk> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
201 lines
6.7 KiB
C
201 lines
6.7 KiB
C
/*
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* arch/arm/include/asm/hardware/cache-l2x0.h
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*
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* Copyright (C) 2007 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARM_HARDWARE_L2X0_H
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#define __ASM_ARM_HARDWARE_L2X0_H
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#include <linux/errno.h>
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#define L2X0_CACHE_ID 0x000
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#define L2X0_CACHE_TYPE 0x004
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#define L2X0_CTRL 0x100
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#define L2X0_AUX_CTRL 0x104
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#define L310_TAG_LATENCY_CTRL 0x108
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#define L310_DATA_LATENCY_CTRL 0x10C
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#define L2X0_EVENT_CNT_CTRL 0x200
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#define L2X0_EVENT_CNT1_CFG 0x204
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#define L2X0_EVENT_CNT0_CFG 0x208
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#define L2X0_EVENT_CNT1_VAL 0x20C
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#define L2X0_EVENT_CNT0_VAL 0x210
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#define L2X0_INTR_MASK 0x214
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#define L2X0_MASKED_INTR_STAT 0x218
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#define L2X0_RAW_INTR_STAT 0x21C
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#define L2X0_INTR_CLEAR 0x220
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#define L2X0_CACHE_SYNC 0x730
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#define L2X0_DUMMY_REG 0x740
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#define L2X0_INV_LINE_PA 0x770
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#define L2X0_INV_WAY 0x77C
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#define L2X0_CLEAN_LINE_PA 0x7B0
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#define L2X0_CLEAN_LINE_IDX 0x7B8
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#define L2X0_CLEAN_WAY 0x7BC
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#define L2X0_CLEAN_INV_LINE_PA 0x7F0
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#define L2X0_CLEAN_INV_LINE_IDX 0x7F8
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#define L2X0_CLEAN_INV_WAY 0x7FC
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/*
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* The lockdown registers repeat 8 times for L310, the L210 has only one
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* D and one I lockdown register at 0x0900 and 0x0904.
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*/
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#define L2X0_LOCKDOWN_WAY_D_BASE 0x900
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#define L2X0_LOCKDOWN_WAY_I_BASE 0x904
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#define L2X0_LOCKDOWN_STRIDE 0x08
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#define L310_ADDR_FILTER_START 0xC00
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#define L310_ADDR_FILTER_END 0xC04
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#define L2X0_TEST_OPERATION 0xF00
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#define L2X0_LINE_DATA 0xF10
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#define L2X0_LINE_TAG 0xF30
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#define L2X0_DEBUG_CTRL 0xF40
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#define L310_PREFETCH_CTRL 0xF60
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#define L310_POWER_CTRL 0xF80
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#define L310_DYNAMIC_CLK_GATING_EN (1 << 1)
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#define L310_STNDBY_MODE_EN (1 << 0)
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/* Registers shifts and masks */
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#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
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#define L2X0_CACHE_ID_PART_L210 (1 << 6)
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#define L2X0_CACHE_ID_PART_L220 (2 << 6)
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#define L2X0_CACHE_ID_PART_L310 (3 << 6)
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#define L2X0_CACHE_ID_RTL_MASK 0x3f
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#define L210_CACHE_ID_RTL_R0P2_02 0x00
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#define L210_CACHE_ID_RTL_R0P1 0x01
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#define L210_CACHE_ID_RTL_R0P2_01 0x02
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#define L210_CACHE_ID_RTL_R0P3 0x03
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#define L210_CACHE_ID_RTL_R0P4 0x0b
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#define L210_CACHE_ID_RTL_R0P5 0x0f
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#define L220_CACHE_ID_RTL_R1P7_01REL0 0x06
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#define L310_CACHE_ID_RTL_R0P0 0x00
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#define L310_CACHE_ID_RTL_R1P0 0x02
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#define L310_CACHE_ID_RTL_R2P0 0x04
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#define L310_CACHE_ID_RTL_R3P0 0x05
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#define L310_CACHE_ID_RTL_R3P1 0x06
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#define L310_CACHE_ID_RTL_R3P1_50REL0 0x07
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#define L310_CACHE_ID_RTL_R3P2 0x08
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#define L310_CACHE_ID_RTL_R3P3 0x09
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#define L2X0_EVENT_CNT_CTRL_ENABLE BIT(0)
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#define L2X0_EVENT_CNT_CFG_SRC_SHIFT 2
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#define L2X0_EVENT_CNT_CFG_SRC_MASK 0xf
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#define L2X0_EVENT_CNT_CFG_SRC_DISABLED 0
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#define L2X0_EVENT_CNT_CFG_INT_DISABLED 0
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#define L2X0_EVENT_CNT_CFG_INT_INCR 1
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#define L2X0_EVENT_CNT_CFG_INT_OVERFLOW 2
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/* L2C auxiliary control register - bits common to L2C-210/220/310 */
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#define L2C_AUX_CTRL_WAY_SIZE_SHIFT 17
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#define L2C_AUX_CTRL_WAY_SIZE_MASK (7 << 17)
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#define L2C_AUX_CTRL_WAY_SIZE(n) ((n) << 17)
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#define L2C_AUX_CTRL_EVTMON_ENABLE BIT(20)
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#define L2C_AUX_CTRL_PARITY_ENABLE BIT(21)
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#define L2C_AUX_CTRL_SHARED_OVERRIDE BIT(22)
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/* L2C-210/220 common bits */
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#define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0
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#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK (7 << 0)
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#define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3
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#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (7 << 3)
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#define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6
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#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (7 << 6)
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#define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9
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#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (7 << 9)
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#define L2X0_AUX_CTRL_ASSOC_SHIFT 13
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#define L2X0_AUX_CTRL_ASSOC_MASK (15 << 13)
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/* L2C-210 specific bits */
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#define L210_AUX_CTRL_WRAP_DISABLE BIT(12)
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#define L210_AUX_CTRL_WA_OVERRIDE BIT(23)
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#define L210_AUX_CTRL_EXCLUSIVE_ABORT BIT(24)
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/* L2C-220 specific bits */
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#define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
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#define L220_AUX_CTRL_FWA_SHIFT 23
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#define L220_AUX_CTRL_FWA_MASK (3 << 23)
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#define L220_AUX_CTRL_NS_LOCKDOWN BIT(26)
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#define L220_AUX_CTRL_NS_INT_CTRL BIT(27)
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/* L2C-310 specific bits */
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#define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */
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#define L310_AUX_CTRL_HIGHPRIO_SO_DEV BIT(10) /* R2P0+ */
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#define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */
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#define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
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#define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16)
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#define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */
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#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26)
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#define L310_AUX_CTRL_NS_INT_CTRL BIT(27)
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#define L310_AUX_CTRL_DATA_PREFETCH BIT(28)
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#define L310_AUX_CTRL_INSTR_PREFETCH BIT(29)
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#define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */
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#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
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#define L310_LATENCY_CTRL_RD(n) ((n) << 4)
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#define L310_LATENCY_CTRL_WR(n) ((n) << 8)
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#define L310_ADDR_FILTER_EN 1
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#define L310_PREFETCH_CTRL_OFFSET_MASK 0x1f
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#define L310_PREFETCH_CTRL_DBL_LINEFILL_INCR BIT(23)
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#define L310_PREFETCH_CTRL_PREFETCH_DROP BIT(24)
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#define L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP BIT(27)
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#define L310_PREFETCH_CTRL_DATA_PREFETCH BIT(28)
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#define L310_PREFETCH_CTRL_INSTR_PREFETCH BIT(29)
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#define L310_PREFETCH_CTRL_DBL_LINEFILL BIT(30)
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#define L2X0_CTRL_EN 1
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#define L2X0_WAY_SIZE_SHIFT 3
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#ifndef __ASSEMBLY__
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extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask);
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#if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF)
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extern int l2x0_of_init(u32 aux_val, u32 aux_mask);
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#else
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static inline int l2x0_of_init(u32 aux_val, u32 aux_mask)
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{
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return -ENODEV;
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}
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#endif
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#ifdef CONFIG_CACHE_L2X0_PMU
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void l2x0_pmu_register(void __iomem *base, u32 part);
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void l2x0_pmu_suspend(void);
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void l2x0_pmu_resume(void);
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#else
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static inline void l2x0_pmu_register(void __iomem *base, u32 part) {}
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static inline void l2x0_pmu_suspend(void) {}
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static inline void l2x0_pmu_resume(void) {}
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#endif
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struct l2x0_regs {
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unsigned long phy_base;
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unsigned long aux_ctrl;
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/*
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* Whether the following registers need to be saved/restored
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* depends on platform
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*/
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unsigned long tag_latency;
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unsigned long data_latency;
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unsigned long filter_start;
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unsigned long filter_end;
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unsigned long prefetch_ctrl;
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unsigned long pwr_ctrl;
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unsigned long ctrl;
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unsigned long aux2_ctrl;
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};
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extern struct l2x0_regs l2x0_saved_regs;
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#endif /* __ASSEMBLY__ */
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#endif
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