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6227e9f0e9
Now when we have properly working performance counters in nSIM
even with interrupt support (fix should be a part of upcoming
nSIM engineering build 2016.12-005) we may enable perf support
by default for all platforms that use nSIM for ARC cores simulation.
Note 1: PCT node was missing for some reason in nsimosci.dts
while all other nSIM-related .dts files already had
PCT node for quite some time, so adding it now.
Note 2: All defconfigs were regenerated with "make savedefconfig"
which led to some clean-ups in nsimosci_hs_smp_defconfig:
CONFIG_FRAMEBUFFER_CONSOLE=y was removed because it is
automatically selected now by DRM.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
92 lines
1.9 KiB
Plaintext
92 lines
1.9 KiB
Plaintext
/*
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* Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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/include/ "skeleton.dtsi"
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/ {
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model = "snps,nsimosci";
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compatible = "snps,nsimosci";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&core_intc>;
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chosen {
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/* this is for console on PGU */
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/* bootargs = "console=tty0 consoleblank=0"; */
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/* this is for console on serial */
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bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblank=0 debug video=640x480-24";
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};
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aliases {
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serial0 = &uart0;
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};
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fpga {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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/* child and parent address space 1:1 mapped */
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ranges;
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core_clk: core_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <20000000>;
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};
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core_intc: interrupt-controller {
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compatible = "snps,arc700-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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uart0: serial@f0000000 {
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compatible = "ns8250";
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reg = <0xf0000000 0x2000>;
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interrupts = <11>;
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clock-frequency = <3686400>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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no-loopback-test = <1>;
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};
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pguclk: pguclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25175000>;
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};
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pgu@f9000000 {
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compatible = "snps,arcpgu";
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reg = <0xf9000000 0x400>;
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clocks = <&pguclk>;
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clock-names = "pxlclk";
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};
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ps2: ps2@f9001000 {
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compatible = "snps,arc_ps2";
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reg = <0xf9000400 0x14>;
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interrupts = <13>;
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interrupt-names = "arc_ps2_irq";
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};
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eth0: ethernet@f0003000 {
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compatible = "ezchip,nps-mgt-enet";
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reg = <0xf0003000 0x44>;
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interrupts = <7>;
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};
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arcpct0: pct {
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compatible = "snps,arc700-pct";
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};
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};
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};
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