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96a388de5d
Move the headers to include/asm-x86 and fixup the header install make rules Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
#ifndef __X86_64_MMU_CONTEXT_H
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#define __X86_64_MMU_CONTEXT_H
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#include <asm/desc.h>
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#include <asm/atomic.h>
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#include <asm/pgalloc.h>
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#include <asm/pda.h>
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#include <asm/pgtable.h>
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#include <asm/tlbflush.h>
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#include <asm-generic/mm_hooks.h>
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/*
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* possibly do the LDT unload here?
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*/
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int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
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void destroy_context(struct mm_struct *mm);
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static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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#ifdef CONFIG_SMP
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if (read_pda(mmu_state) == TLBSTATE_OK)
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write_pda(mmu_state, TLBSTATE_LAZY);
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#endif
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}
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static inline void load_cr3(pgd_t *pgd)
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{
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asm volatile("movq %0,%%cr3" :: "r" (__pa(pgd)) : "memory");
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}
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static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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unsigned cpu = smp_processor_id();
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if (likely(prev != next)) {
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/* stop flush ipis for the previous mm */
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cpu_clear(cpu, prev->cpu_vm_mask);
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#ifdef CONFIG_SMP
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write_pda(mmu_state, TLBSTATE_OK);
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write_pda(active_mm, next);
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#endif
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cpu_set(cpu, next->cpu_vm_mask);
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load_cr3(next->pgd);
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if (unlikely(next->context.ldt != prev->context.ldt))
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load_LDT_nolock(&next->context, cpu);
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}
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#ifdef CONFIG_SMP
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else {
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write_pda(mmu_state, TLBSTATE_OK);
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if (read_pda(active_mm) != next)
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out_of_line_bug();
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if (!cpu_test_and_set(cpu, next->cpu_vm_mask)) {
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/* We were in lazy tlb mode and leave_mm disabled
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* tlb flush IPI delivery. We must reload CR3
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* to make sure to use no freed page tables.
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*/
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load_cr3(next->pgd);
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load_LDT_nolock(&next->context, cpu);
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}
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}
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#endif
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}
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#define deactivate_mm(tsk,mm) do { \
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load_gs_index(0); \
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asm volatile("movl %0,%%fs"::"r"(0)); \
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} while(0)
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#define activate_mm(prev, next) \
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switch_mm((prev),(next),NULL)
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#endif
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