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963fcd4095
As the firmware (or the hypervisor) may have disabled SRE access, check that SRE can actually be enabled before declaring that we do have that capability. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
120 lines
3.0 KiB
C
120 lines
3.0 KiB
C
/*
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* Contains CPU feature definitions
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*
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* Copyright (C) 2015 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#define pr_fmt(fmt) "alternatives: " fmt
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#include <linux/types.h>
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#include <asm/cpu.h>
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#include <asm/cpufeature.h>
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#include <asm/processor.h>
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#include <linux/irqchip/arm-gic-v3.h>
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static bool
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feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
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{
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int val = cpuid_feature_extract_field(reg, entry->field_pos);
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return val >= entry->min_field_value;
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}
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#define __ID_FEAT_CHK(reg) \
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static bool __maybe_unused \
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has_##reg##_feature(const struct arm64_cpu_capabilities *entry) \
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{ \
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u64 val; \
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\
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val = read_cpuid(reg##_el1); \
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return feature_matches(val, entry); \
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}
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__ID_FEAT_CHK(id_aa64pfr0);
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__ID_FEAT_CHK(id_aa64mmfr1);
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__ID_FEAT_CHK(id_aa64isar0);
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static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)
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{
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bool has_sre;
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if (!has_id_aa64pfr0_feature(entry))
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return false;
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has_sre = gic_enable_sre();
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if (!has_sre)
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pr_warn_once("%s present but disabled by higher exception level\n",
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entry->desc);
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return has_sre;
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}
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static const struct arm64_cpu_capabilities arm64_features[] = {
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{
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.desc = "GIC system register CPU interface",
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.capability = ARM64_HAS_SYSREG_GIC_CPUIF,
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.matches = has_useable_gicv3_cpuif,
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.field_pos = 24,
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.min_field_value = 1,
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},
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#ifdef CONFIG_ARM64_PAN
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{
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.desc = "Privileged Access Never",
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.capability = ARM64_HAS_PAN,
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.matches = has_id_aa64mmfr1_feature,
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.field_pos = 20,
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.min_field_value = 1,
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.enable = cpu_enable_pan,
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},
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#endif /* CONFIG_ARM64_PAN */
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#if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
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{
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.desc = "LSE atomic instructions",
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.capability = ARM64_HAS_LSE_ATOMICS,
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.matches = has_id_aa64isar0_feature,
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.field_pos = 20,
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.min_field_value = 2,
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},
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#endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
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{},
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};
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void check_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
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const char *info)
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{
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int i;
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for (i = 0; caps[i].desc; i++) {
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if (!caps[i].matches(&caps[i]))
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continue;
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if (!cpus_have_cap(caps[i].capability))
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pr_info("%s %s\n", info, caps[i].desc);
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cpus_set_cap(caps[i].capability);
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}
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/* second pass allows enable() to consider interacting capabilities */
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for (i = 0; caps[i].desc; i++) {
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if (cpus_have_cap(caps[i].capability) && caps[i].enable)
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caps[i].enable();
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}
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}
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void check_local_cpu_features(void)
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{
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check_cpu_capabilities(arm64_features, "detected feature:");
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}
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