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de862b488e
The TX49XX has the prefetch instruction. It supports only Pref_Load
(hint 0). Actually changes in this patch except for Kconfig are not
have any effects, I added these changes to prevent misuse of unsupported
hints.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
493 lines
11 KiB
C
493 lines
11 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org)
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/proc_fs.h>
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#include <asm/cacheops.h>
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#include <asm/inst.h>
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#include <asm/io.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/prefetch.h>
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#include <asm/system.h>
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#include <asm/bootinfo.h>
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#include <asm/mipsregs.h>
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#include <asm/mmu_context.h>
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#include <asm/cpu.h>
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#include <asm/war.h>
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#define half_scache_line_size() (cpu_scache_line_size() >> 1)
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#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
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#define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
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/*
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* Maximum sizes:
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*
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* R4000 128 bytes S-cache: 0x58 bytes
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* R4600 v1.7: 0x5c bytes
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* R4600 v2.0: 0x60 bytes
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* With prefetching, 16 byte strides 0xa0 bytes
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*/
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static unsigned int clear_page_array[0x130 / 4];
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void clear_page(void * page) __attribute__((alias("clear_page_array")));
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EXPORT_SYMBOL(clear_page);
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/*
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* Maximum sizes:
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*
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* R4000 128 bytes S-cache: 0x11c bytes
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* R4600 v1.7: 0x080 bytes
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* R4600 v2.0: 0x07c bytes
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* With prefetching, 16 byte strides 0x0b8 bytes
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*/
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static unsigned int copy_page_array[0x148 / 4];
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void copy_page(void *to, void *from) __attribute__((alias("copy_page_array")));
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EXPORT_SYMBOL(copy_page);
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/*
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* This is suboptimal for 32-bit kernels; we assume that R10000 is only used
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* with 64-bit kernels. The prefetch offsets have been experimentally tuned
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* an Origin 200.
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*/
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static int pref_offset_clear __initdata = 512;
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static int pref_offset_copy __initdata = 256;
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static unsigned int pref_src_mode __initdata;
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static unsigned int pref_dst_mode __initdata;
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static int load_offset __initdata;
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static int store_offset __initdata;
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static unsigned int __initdata *dest, *epc;
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static unsigned int instruction_pending;
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static union mips_instruction delayed_mi;
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static void __init emit_instruction(union mips_instruction mi)
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{
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if (instruction_pending)
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*epc++ = delayed_mi.word;
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instruction_pending = 1;
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delayed_mi = mi;
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}
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static inline void flush_delay_slot_or_nop(void)
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{
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if (instruction_pending) {
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*epc++ = delayed_mi.word;
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instruction_pending = 0;
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return;
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}
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*epc++ = 0;
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}
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static inline unsigned int *label(void)
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{
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if (instruction_pending) {
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*epc++ = delayed_mi.word;
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instruction_pending = 0;
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}
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return epc;
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}
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static inline void build_insn_word(unsigned int word)
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{
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union mips_instruction mi;
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mi.word = word;
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emit_instruction(mi);
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}
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static inline void build_nop(void)
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{
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build_insn_word(0); /* nop */
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}
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static inline void build_src_pref(int advance)
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{
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if (!(load_offset & (cpu_dcache_line_size() - 1)) && advance) {
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union mips_instruction mi;
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mi.i_format.opcode = pref_op;
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mi.i_format.rs = 5; /* $a1 */
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mi.i_format.rt = pref_src_mode;
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mi.i_format.simmediate = load_offset + advance;
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emit_instruction(mi);
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}
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}
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static inline void __build_load_reg(int reg)
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{
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union mips_instruction mi;
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unsigned int width;
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if (cpu_has_64bit_gp_regs) {
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mi.i_format.opcode = ld_op;
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width = 8;
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} else {
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mi.i_format.opcode = lw_op;
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width = 4;
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}
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mi.i_format.rs = 5; /* $a1 */
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mi.i_format.rt = reg; /* $reg */
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mi.i_format.simmediate = load_offset;
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load_offset += width;
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emit_instruction(mi);
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}
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static inline void build_load_reg(int reg)
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{
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if (cpu_has_prefetch)
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build_src_pref(pref_offset_copy);
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__build_load_reg(reg);
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}
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static inline void build_dst_pref(int advance)
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{
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if (!(store_offset & (cpu_dcache_line_size() - 1)) && advance) {
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union mips_instruction mi;
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mi.i_format.opcode = pref_op;
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mi.i_format.rs = 4; /* $a0 */
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mi.i_format.rt = pref_dst_mode;
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mi.i_format.simmediate = store_offset + advance;
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emit_instruction(mi);
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}
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}
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static inline void build_cdex_s(void)
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{
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union mips_instruction mi;
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if ((store_offset & (cpu_scache_line_size() - 1)))
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return;
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mi.c_format.opcode = cache_op;
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mi.c_format.rs = 4; /* $a0 */
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mi.c_format.c_op = 3; /* Create Dirty Exclusive */
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mi.c_format.cache = 3; /* Secondary Data Cache */
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mi.c_format.simmediate = store_offset;
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emit_instruction(mi);
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}
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static inline void build_cdex_p(void)
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{
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union mips_instruction mi;
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if (store_offset & (cpu_dcache_line_size() - 1))
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return;
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if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
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build_nop();
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build_nop();
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build_nop();
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build_nop();
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}
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if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
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build_insn_word(0x3c01a000); /* lui $at, 0xa000 */
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mi.c_format.opcode = cache_op;
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mi.c_format.rs = 4; /* $a0 */
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mi.c_format.c_op = 3; /* Create Dirty Exclusive */
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mi.c_format.cache = 1; /* Data Cache */
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mi.c_format.simmediate = store_offset;
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emit_instruction(mi);
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}
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static void __init __build_store_reg(int reg)
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{
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union mips_instruction mi;
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unsigned int width;
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if (cpu_has_64bit_gp_regs ||
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(cpu_has_64bit_zero_reg && reg == 0)) {
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mi.i_format.opcode = sd_op;
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width = 8;
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} else {
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mi.i_format.opcode = sw_op;
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width = 4;
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}
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mi.i_format.rs = 4; /* $a0 */
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mi.i_format.rt = reg; /* $reg */
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mi.i_format.simmediate = store_offset;
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store_offset += width;
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emit_instruction(mi);
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}
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static inline void build_store_reg(int reg)
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{
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if (cpu_has_prefetch)
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if (reg)
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build_dst_pref(pref_offset_copy);
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else
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build_dst_pref(pref_offset_clear);
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else if (cpu_has_cache_cdex_s)
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build_cdex_s();
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else if (cpu_has_cache_cdex_p)
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build_cdex_p();
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__build_store_reg(reg);
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}
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static inline void build_addiu_a2_a0(unsigned long offset)
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{
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union mips_instruction mi;
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BUG_ON(offset > 0x7fff);
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mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op;
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mi.i_format.rs = 4; /* $a0 */
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mi.i_format.rt = 6; /* $a2 */
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mi.i_format.simmediate = offset;
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emit_instruction(mi);
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}
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static inline void build_addiu_a1(unsigned long offset)
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{
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union mips_instruction mi;
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BUG_ON(offset > 0x7fff);
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mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op;
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mi.i_format.rs = 5; /* $a1 */
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mi.i_format.rt = 5; /* $a1 */
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mi.i_format.simmediate = offset;
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load_offset -= offset;
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emit_instruction(mi);
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}
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static inline void build_addiu_a0(unsigned long offset)
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{
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union mips_instruction mi;
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BUG_ON(offset > 0x7fff);
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mi.i_format.opcode = cpu_has_64bit_gp_regs ? daddiu_op : addiu_op;
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mi.i_format.rs = 4; /* $a0 */
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mi.i_format.rt = 4; /* $a0 */
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mi.i_format.simmediate = offset;
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store_offset -= offset;
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emit_instruction(mi);
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}
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static inline void build_bne(unsigned int *dest)
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{
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union mips_instruction mi;
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mi.i_format.opcode = bne_op;
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mi.i_format.rs = 6; /* $a2 */
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mi.i_format.rt = 4; /* $a0 */
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mi.i_format.simmediate = dest - epc - 1;
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*epc++ = mi.word;
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flush_delay_slot_or_nop();
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}
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static inline void build_jr_ra(void)
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{
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union mips_instruction mi;
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mi.r_format.opcode = spec_op;
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mi.r_format.rs = 31;
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mi.r_format.rt = 0;
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mi.r_format.rd = 0;
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mi.r_format.re = 0;
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mi.r_format.func = jr_op;
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*epc++ = mi.word;
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flush_delay_slot_or_nop();
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}
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void __init build_clear_page(void)
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{
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unsigned int loop_start;
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epc = (unsigned int *) &clear_page_array;
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instruction_pending = 0;
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store_offset = 0;
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if (cpu_has_prefetch) {
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switch (current_cpu_data.cputype) {
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case CPU_TX49XX:
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/* TX49 supports only Pref_Load */
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pref_offset_clear = 0;
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pref_offset_copy = 0;
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break;
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case CPU_RM9000:
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/*
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* As a workaround for erratum G105 which make the
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* PrepareForStore hint unusable we fall back to
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* StoreRetained on the RM9000. Once it is known which
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* versions of the RM9000 we'll be able to condition-
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* alize this.
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*/
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case CPU_R10000:
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case CPU_R12000:
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pref_src_mode = Pref_LoadStreamed;
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pref_dst_mode = Pref_StoreStreamed;
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break;
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default:
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pref_src_mode = Pref_LoadStreamed;
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pref_dst_mode = Pref_PrepareForStore;
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break;
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}
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}
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build_addiu_a2_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_clear : 0));
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if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
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build_insn_word(0x3c01a000); /* lui $at, 0xa000 */
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dest = label();
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do {
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build_store_reg(0);
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build_store_reg(0);
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build_store_reg(0);
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build_store_reg(0);
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} while (store_offset < half_scache_line_size());
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build_addiu_a0(2 * store_offset);
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loop_start = store_offset;
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do {
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build_store_reg(0);
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build_store_reg(0);
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build_store_reg(0);
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build_store_reg(0);
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} while ((store_offset - loop_start) < half_scache_line_size());
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build_bne(dest);
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if (cpu_has_prefetch && pref_offset_clear) {
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build_addiu_a2_a0(pref_offset_clear);
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dest = label();
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loop_start = store_offset;
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do {
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__build_store_reg(0);
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__build_store_reg(0);
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__build_store_reg(0);
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__build_store_reg(0);
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} while ((store_offset - loop_start) < half_scache_line_size());
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build_addiu_a0(2 * store_offset);
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loop_start = store_offset;
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do {
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__build_store_reg(0);
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__build_store_reg(0);
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__build_store_reg(0);
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__build_store_reg(0);
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} while ((store_offset - loop_start) < half_scache_line_size());
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build_bne(dest);
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}
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build_jr_ra();
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BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array));
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}
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void __init build_copy_page(void)
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{
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unsigned int loop_start;
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epc = (unsigned int *) ©_page_array;
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store_offset = load_offset = 0;
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instruction_pending = 0;
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build_addiu_a2_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_copy : 0));
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if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
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build_insn_word(0x3c01a000); /* lui $at, 0xa000 */
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dest = label();
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loop_start = store_offset;
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do {
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build_load_reg( 8);
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build_load_reg( 9);
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build_load_reg(10);
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build_load_reg(11);
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build_store_reg( 8);
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build_store_reg( 9);
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build_store_reg(10);
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build_store_reg(11);
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} while ((store_offset - loop_start) < half_scache_line_size());
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build_addiu_a0(2 * store_offset);
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build_addiu_a1(2 * load_offset);
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loop_start = store_offset;
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do {
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build_load_reg( 8);
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build_load_reg( 9);
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build_load_reg(10);
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build_load_reg(11);
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build_store_reg( 8);
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build_store_reg( 9);
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build_store_reg(10);
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build_store_reg(11);
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} while ((store_offset - loop_start) < half_scache_line_size());
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build_bne(dest);
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if (cpu_has_prefetch && pref_offset_copy) {
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build_addiu_a2_a0(pref_offset_copy);
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dest = label();
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loop_start = store_offset;
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do {
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__build_load_reg( 8);
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__build_load_reg( 9);
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__build_load_reg(10);
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__build_load_reg(11);
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__build_store_reg( 8);
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__build_store_reg( 9);
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__build_store_reg(10);
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__build_store_reg(11);
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} while ((store_offset - loop_start) < half_scache_line_size());
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build_addiu_a0(2 * store_offset);
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build_addiu_a1(2 * load_offset);
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loop_start = store_offset;
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do {
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__build_load_reg( 8);
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__build_load_reg( 9);
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__build_load_reg(10);
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__build_load_reg(11);
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__build_store_reg( 8);
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__build_store_reg( 9);
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__build_store_reg(10);
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__build_store_reg(11);
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} while ((store_offset - loop_start) < half_scache_line_size());
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build_bne(dest);
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}
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build_jr_ra();
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BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array));
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}
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