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7e6eae24da
Signed-off-by: Xingyou Chen <rockrush@rockwork.org> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Link: https://lore.kernel.org/r/20240317055556.9449-1-rockrush@rockwork.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
228 lines
5.9 KiB
ArmAsm
228 lines
5.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2012 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/linkage.h>
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#include <asm/asm.h>
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#include <asm/csr.h>
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#include <asm/asm-offsets.h>
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SYM_FUNC_START(__fstate_save)
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li a2, TASK_THREAD_F0
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add a0, a0, a2
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li t1, SR_FS
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csrs CSR_STATUS, t1
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frcsr t0
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fsd f0, TASK_THREAD_F0_F0(a0)
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fsd f1, TASK_THREAD_F1_F0(a0)
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fsd f2, TASK_THREAD_F2_F0(a0)
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fsd f3, TASK_THREAD_F3_F0(a0)
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fsd f4, TASK_THREAD_F4_F0(a0)
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fsd f5, TASK_THREAD_F5_F0(a0)
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fsd f6, TASK_THREAD_F6_F0(a0)
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fsd f7, TASK_THREAD_F7_F0(a0)
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fsd f8, TASK_THREAD_F8_F0(a0)
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fsd f9, TASK_THREAD_F9_F0(a0)
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fsd f10, TASK_THREAD_F10_F0(a0)
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fsd f11, TASK_THREAD_F11_F0(a0)
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fsd f12, TASK_THREAD_F12_F0(a0)
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fsd f13, TASK_THREAD_F13_F0(a0)
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fsd f14, TASK_THREAD_F14_F0(a0)
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fsd f15, TASK_THREAD_F15_F0(a0)
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fsd f16, TASK_THREAD_F16_F0(a0)
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fsd f17, TASK_THREAD_F17_F0(a0)
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fsd f18, TASK_THREAD_F18_F0(a0)
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fsd f19, TASK_THREAD_F19_F0(a0)
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fsd f20, TASK_THREAD_F20_F0(a0)
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fsd f21, TASK_THREAD_F21_F0(a0)
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fsd f22, TASK_THREAD_F22_F0(a0)
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fsd f23, TASK_THREAD_F23_F0(a0)
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fsd f24, TASK_THREAD_F24_F0(a0)
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fsd f25, TASK_THREAD_F25_F0(a0)
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fsd f26, TASK_THREAD_F26_F0(a0)
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fsd f27, TASK_THREAD_F27_F0(a0)
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fsd f28, TASK_THREAD_F28_F0(a0)
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fsd f29, TASK_THREAD_F29_F0(a0)
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fsd f30, TASK_THREAD_F30_F0(a0)
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fsd f31, TASK_THREAD_F31_F0(a0)
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sw t0, TASK_THREAD_FCSR_F0(a0)
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csrc CSR_STATUS, t1
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ret
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SYM_FUNC_END(__fstate_save)
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SYM_FUNC_START(__fstate_restore)
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li a2, TASK_THREAD_F0
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add a0, a0, a2
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li t1, SR_FS
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lw t0, TASK_THREAD_FCSR_F0(a0)
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csrs CSR_STATUS, t1
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fld f0, TASK_THREAD_F0_F0(a0)
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fld f1, TASK_THREAD_F1_F0(a0)
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fld f2, TASK_THREAD_F2_F0(a0)
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fld f3, TASK_THREAD_F3_F0(a0)
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fld f4, TASK_THREAD_F4_F0(a0)
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fld f5, TASK_THREAD_F5_F0(a0)
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fld f6, TASK_THREAD_F6_F0(a0)
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fld f7, TASK_THREAD_F7_F0(a0)
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fld f8, TASK_THREAD_F8_F0(a0)
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fld f9, TASK_THREAD_F9_F0(a0)
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fld f10, TASK_THREAD_F10_F0(a0)
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fld f11, TASK_THREAD_F11_F0(a0)
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fld f12, TASK_THREAD_F12_F0(a0)
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fld f13, TASK_THREAD_F13_F0(a0)
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fld f14, TASK_THREAD_F14_F0(a0)
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fld f15, TASK_THREAD_F15_F0(a0)
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fld f16, TASK_THREAD_F16_F0(a0)
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fld f17, TASK_THREAD_F17_F0(a0)
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fld f18, TASK_THREAD_F18_F0(a0)
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fld f19, TASK_THREAD_F19_F0(a0)
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fld f20, TASK_THREAD_F20_F0(a0)
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fld f21, TASK_THREAD_F21_F0(a0)
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fld f22, TASK_THREAD_F22_F0(a0)
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fld f23, TASK_THREAD_F23_F0(a0)
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fld f24, TASK_THREAD_F24_F0(a0)
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fld f25, TASK_THREAD_F25_F0(a0)
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fld f26, TASK_THREAD_F26_F0(a0)
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fld f27, TASK_THREAD_F27_F0(a0)
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fld f28, TASK_THREAD_F28_F0(a0)
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fld f29, TASK_THREAD_F29_F0(a0)
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fld f30, TASK_THREAD_F30_F0(a0)
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fld f31, TASK_THREAD_F31_F0(a0)
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fscsr t0
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csrc CSR_STATUS, t1
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ret
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SYM_FUNC_END(__fstate_restore)
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#define get_f32(which) fmv.x.s a0, which; j 2f
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#define put_f32(which) fmv.s.x which, a1; j 2f
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#if __riscv_xlen == 64
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# define get_f64(which) fmv.x.d a0, which; j 2f
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# define put_f64(which) fmv.d.x which, a1; j 2f
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#else
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# define get_f64(which) fsd which, 0(a1); j 2f
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# define put_f64(which) fld which, 0(a1); j 2f
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#endif
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.macro fp_access_prologue
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/*
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* Compute jump offset to store the correct FP register since we don't
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* have indirect FP register access
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*/
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sll t0, a0, 3
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la t2, 1f
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add t0, t0, t2
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li t1, SR_FS
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csrs CSR_STATUS, t1
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jr t0
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1:
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.endm
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.macro fp_access_epilogue
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2:
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csrc CSR_STATUS, t1
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ret
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.endm
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#define fp_access_body(__access_func) \
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__access_func(f0); \
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__access_func(f1); \
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__access_func(f2); \
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__access_func(f3); \
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__access_func(f4); \
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__access_func(f5); \
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__access_func(f6); \
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__access_func(f7); \
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__access_func(f8); \
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__access_func(f9); \
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__access_func(f10); \
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__access_func(f11); \
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__access_func(f12); \
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__access_func(f13); \
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__access_func(f14); \
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__access_func(f15); \
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__access_func(f16); \
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__access_func(f17); \
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__access_func(f18); \
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__access_func(f19); \
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__access_func(f20); \
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__access_func(f21); \
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__access_func(f22); \
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__access_func(f23); \
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__access_func(f24); \
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__access_func(f25); \
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__access_func(f26); \
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__access_func(f27); \
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__access_func(f28); \
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__access_func(f29); \
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__access_func(f30); \
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__access_func(f31)
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#ifdef CONFIG_RISCV_MISALIGNED
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/*
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* Disable compressed instructions set to keep a constant offset between FP
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* load/store/move instructions
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*/
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.option norvc
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/*
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* put_f32_reg - Set a FP register from a register containing the value
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* a0 = FP register index to be set
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* a1 = value to be loaded in the FP register
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*/
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SYM_FUNC_START(put_f32_reg)
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fp_access_prologue
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fp_access_body(put_f32)
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fp_access_epilogue
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SYM_FUNC_END(put_f32_reg)
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/*
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* get_f32_reg - Get a FP register value and return it
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* a0 = FP register index to be retrieved
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*/
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SYM_FUNC_START(get_f32_reg)
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fp_access_prologue
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fp_access_body(get_f32)
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fp_access_epilogue
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SYM_FUNC_END(get_f32_reg)
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/*
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* put_f64_reg - Set a 64 bits FP register from a value or a pointer.
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* a0 = FP register index to be set
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* a1 = value/pointer to be loaded in the FP register (when xlen == 32 bits, we
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* load the value to a pointer).
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*/
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SYM_FUNC_START(put_f64_reg)
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fp_access_prologue
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fp_access_body(put_f64)
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fp_access_epilogue
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SYM_FUNC_END(put_f64_reg)
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/*
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* get_f64_reg - Get a 64 bits FP register value and returned it or store it to
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* a pointer.
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* a0 = FP register index to be retrieved
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* a1 = If xlen == 32, pointer which should be loaded with the FP register value
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* or unused if xlen == 64. In which case the FP register value is returned
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* through a0
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*/
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SYM_FUNC_START(get_f64_reg)
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fp_access_prologue
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fp_access_body(get_f64)
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fp_access_epilogue
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SYM_FUNC_END(get_f64_reg)
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#endif /* CONFIG_RISCV_MISALIGNED */
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