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The majority of this patch was created by the following script: *** ASM=arch/sparc/include/asm mkdir -p $ASM git mv include/asm-sparc64/ftrace.h $ASM git rm include/asm-sparc64/* git mv include/asm-sparc/* $ASM sed -ie 's/asm-sparc64/asm/g' $ASM/* sed -ie 's/asm-sparc/asm/g' $ASM/* *** The rest was an update of the top-level Makefile to use sparc for header files when sparc64 is being build. And a small fixlet to pick up the correct unistd.h from sparc64 code. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
63 lines
1.4 KiB
C
63 lines
1.4 KiB
C
#ifndef _SPARC64_VISASM_H
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#define _SPARC64_VISASM_H
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/* visasm.h: FPU saving macros for VIS routines
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*
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* Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#include <asm/pstate.h>
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#include <asm/ptrace.h>
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/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
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#define VISEntry \
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rd %fprs, %o5; \
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andcc %o5, (FPRS_FEF|FPRS_DU), %g0; \
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be,pt %icc, 297f; \
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sethi %hi(297f), %g7; \
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sethi %hi(VISenter), %g1; \
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jmpl %g1 + %lo(VISenter), %g0; \
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or %g7, %lo(297f), %g7; \
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297: wr %g0, FPRS_FEF, %fprs; \
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#define VISExit \
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wr %g0, 0, %fprs;
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/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc.
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* Must preserve %o5 between VISEntryHalf and VISExitHalf */
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#define VISEntryHalf \
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rd %fprs, %o5; \
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andcc %o5, FPRS_FEF, %g0; \
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be,pt %icc, 297f; \
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sethi %hi(298f), %g7; \
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sethi %hi(VISenterhalf), %g1; \
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jmpl %g1 + %lo(VISenterhalf), %g0; \
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or %g7, %lo(298f), %g7; \
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clr %o5; \
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297: wr %o5, FPRS_FEF, %fprs; \
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298:
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#define VISExitHalf \
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wr %o5, 0, %fprs;
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#ifndef __ASSEMBLY__
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static inline void save_and_clear_fpu(void) {
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__asm__ __volatile__ (
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" rd %%fprs, %%o5\n"
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" andcc %%o5, %0, %%g0\n"
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" be,pt %%icc, 299f\n"
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" sethi %%hi(298f), %%g7\n"
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" sethi %%hi(VISenter), %%g1\n"
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" jmpl %%g1 + %%lo(VISenter), %%g0\n"
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" or %%g7, %%lo(298f), %%g7\n"
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" 298: wr %%g0, 0, %%fprs\n"
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" 299:\n"
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" " : : "i" (FPRS_FEF|FPRS_DU) :
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"o5", "g1", "g2", "g3", "g7", "cc");
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}
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#endif
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#endif /* _SPARC64_ASI_H */
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