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93c9fce7d5
The pci_save_state() call in vmd_suspend() can be performed by pci_pm_suspend_irq(). This also allows VMD to benefit from the call into pci_prepare_to_sleep(). The pci_restore_state() call in vmd_resume() was restoring state after pci_pm_resume()::pci_restore_standard_config() had already restored state. It's also been suspected that the config state should have been restored before re-requesting IRQs instead of afterwards. Remove the pci_save_state()/pci_restore_state() calls in vmd_suspend()/vmd_resume() to allow proper flow through generic PCI core Power Management code. Link: https://lore.kernel.org/r/20200806210017.5654-1-jonathan.derrick@intel.com Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Kai-Heng Feng <kai.heng.feng@canonical.com> Cc: You-Sheng Yang <vicamo.yang@canonical.com>
841 lines
21 KiB
C
841 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Volume Management Device driver
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* Copyright (c) 2015, Intel Corporation.
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*/
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/pci.h>
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#include <linux/srcu.h>
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#include <linux/rculist.h>
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#include <linux/rcupdate.h>
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#include <asm/irqdomain.h>
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#include <asm/device.h>
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#include <asm/msi.h>
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#include <asm/msidef.h>
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#define VMD_CFGBAR 0
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#define VMD_MEMBAR1 2
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#define VMD_MEMBAR2 4
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#define PCI_REG_VMCAP 0x40
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#define BUS_RESTRICT_CAP(vmcap) (vmcap & 0x1)
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#define PCI_REG_VMCONFIG 0x44
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#define BUS_RESTRICT_CFG(vmcfg) ((vmcfg >> 8) & 0x3)
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#define PCI_REG_VMLOCK 0x70
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#define MB2_SHADOW_EN(vmlock) (vmlock & 0x2)
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#define MB2_SHADOW_OFFSET 0x2000
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#define MB2_SHADOW_SIZE 16
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enum vmd_features {
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/*
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* Device may contain registers which hint the physical location of the
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* membars, in order to allow proper address translation during
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* resource assignment to enable guest virtualization
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*/
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VMD_FEAT_HAS_MEMBAR_SHADOW = (1 << 0),
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/*
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* Device may provide root port configuration information which limits
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* bus numbering
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*/
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VMD_FEAT_HAS_BUS_RESTRICTIONS = (1 << 1),
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/*
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* Device contains physical location shadow registers in
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* vendor-specific capability space
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*/
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VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP = (1 << 2),
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};
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/*
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* Lock for manipulating VMD IRQ lists.
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*/
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static DEFINE_RAW_SPINLOCK(list_lock);
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/**
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* struct vmd_irq - private data to map driver IRQ to the VMD shared vector
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* @node: list item for parent traversal.
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* @irq: back pointer to parent.
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* @enabled: true if driver enabled IRQ
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* @virq: the virtual IRQ value provided to the requesting driver.
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*
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* Every MSI/MSI-X IRQ requested for a device in a VMD domain will be mapped to
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* a VMD IRQ using this structure.
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*/
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struct vmd_irq {
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struct list_head node;
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struct vmd_irq_list *irq;
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bool enabled;
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unsigned int virq;
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};
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/**
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* struct vmd_irq_list - list of driver requested IRQs mapping to a VMD vector
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* @irq_list: the list of irq's the VMD one demuxes to.
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* @srcu: SRCU struct for local synchronization.
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* @count: number of child IRQs assigned to this vector; used to track
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* sharing.
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*/
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struct vmd_irq_list {
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struct list_head irq_list;
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struct srcu_struct srcu;
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unsigned int count;
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};
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struct vmd_dev {
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struct pci_dev *dev;
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spinlock_t cfg_lock;
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char __iomem *cfgbar;
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int msix_count;
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struct vmd_irq_list *irqs;
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struct pci_sysdata sysdata;
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struct resource resources[3];
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struct irq_domain *irq_domain;
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struct pci_bus *bus;
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u8 busn_start;
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};
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static inline struct vmd_dev *vmd_from_bus(struct pci_bus *bus)
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{
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return container_of(bus->sysdata, struct vmd_dev, sysdata);
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}
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static inline unsigned int index_from_irqs(struct vmd_dev *vmd,
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struct vmd_irq_list *irqs)
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{
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return irqs - vmd->irqs;
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}
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/*
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* Drivers managing a device in a VMD domain allocate their own IRQs as before,
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* but the MSI entry for the hardware it's driving will be programmed with a
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* destination ID for the VMD MSI-X table. The VMD muxes interrupts in its
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* domain into one of its own, and the VMD driver de-muxes these for the
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* handlers sharing that VMD IRQ. The vmd irq_domain provides the operations
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* and irq_chip to set this up.
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*/
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static void vmd_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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{
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struct vmd_irq *vmdirq = data->chip_data;
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struct vmd_irq_list *irq = vmdirq->irq;
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struct vmd_dev *vmd = irq_data_get_irq_handler_data(data);
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msg->address_hi = MSI_ADDR_BASE_HI;
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msg->address_lo = MSI_ADDR_BASE_LO |
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MSI_ADDR_DEST_ID(index_from_irqs(vmd, irq));
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msg->data = 0;
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}
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/*
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* We rely on MSI_FLAG_USE_DEF_CHIP_OPS to set the IRQ mask/unmask ops.
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*/
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static void vmd_irq_enable(struct irq_data *data)
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{
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struct vmd_irq *vmdirq = data->chip_data;
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unsigned long flags;
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raw_spin_lock_irqsave(&list_lock, flags);
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WARN_ON(vmdirq->enabled);
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list_add_tail_rcu(&vmdirq->node, &vmdirq->irq->irq_list);
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vmdirq->enabled = true;
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raw_spin_unlock_irqrestore(&list_lock, flags);
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data->chip->irq_unmask(data);
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}
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static void vmd_irq_disable(struct irq_data *data)
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{
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struct vmd_irq *vmdirq = data->chip_data;
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unsigned long flags;
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data->chip->irq_mask(data);
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raw_spin_lock_irqsave(&list_lock, flags);
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if (vmdirq->enabled) {
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list_del_rcu(&vmdirq->node);
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vmdirq->enabled = false;
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}
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raw_spin_unlock_irqrestore(&list_lock, flags);
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}
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/*
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* XXX: Stubbed until we develop acceptable way to not create conflicts with
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* other devices sharing the same vector.
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*/
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static int vmd_irq_set_affinity(struct irq_data *data,
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const struct cpumask *dest, bool force)
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{
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return -EINVAL;
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}
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static struct irq_chip vmd_msi_controller = {
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.name = "VMD-MSI",
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.irq_enable = vmd_irq_enable,
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.irq_disable = vmd_irq_disable,
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.irq_compose_msi_msg = vmd_compose_msi_msg,
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.irq_set_affinity = vmd_irq_set_affinity,
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};
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static irq_hw_number_t vmd_get_hwirq(struct msi_domain_info *info,
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msi_alloc_info_t *arg)
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{
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return 0;
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}
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/*
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* XXX: We can be even smarter selecting the best IRQ once we solve the
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* affinity problem.
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*/
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static struct vmd_irq_list *vmd_next_irq(struct vmd_dev *vmd, struct msi_desc *desc)
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{
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int i, best = 1;
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unsigned long flags;
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if (vmd->msix_count == 1)
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return &vmd->irqs[0];
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/*
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* White list for fast-interrupt handlers. All others will share the
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* "slow" interrupt vector.
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*/
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switch (msi_desc_to_pci_dev(desc)->class) {
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case PCI_CLASS_STORAGE_EXPRESS:
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break;
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default:
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return &vmd->irqs[0];
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}
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raw_spin_lock_irqsave(&list_lock, flags);
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for (i = 1; i < vmd->msix_count; i++)
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if (vmd->irqs[i].count < vmd->irqs[best].count)
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best = i;
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vmd->irqs[best].count++;
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raw_spin_unlock_irqrestore(&list_lock, flags);
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return &vmd->irqs[best];
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}
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static int vmd_msi_init(struct irq_domain *domain, struct msi_domain_info *info,
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unsigned int virq, irq_hw_number_t hwirq,
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msi_alloc_info_t *arg)
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{
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struct msi_desc *desc = arg->desc;
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struct vmd_dev *vmd = vmd_from_bus(msi_desc_to_pci_dev(desc)->bus);
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struct vmd_irq *vmdirq = kzalloc(sizeof(*vmdirq), GFP_KERNEL);
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unsigned int index, vector;
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if (!vmdirq)
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return -ENOMEM;
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INIT_LIST_HEAD(&vmdirq->node);
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vmdirq->irq = vmd_next_irq(vmd, desc);
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vmdirq->virq = virq;
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index = index_from_irqs(vmd, vmdirq->irq);
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vector = pci_irq_vector(vmd->dev, index);
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irq_domain_set_info(domain, virq, vector, info->chip, vmdirq,
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handle_untracked_irq, vmd, NULL);
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return 0;
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}
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static void vmd_msi_free(struct irq_domain *domain,
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struct msi_domain_info *info, unsigned int virq)
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{
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struct vmd_irq *vmdirq = irq_get_chip_data(virq);
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unsigned long flags;
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synchronize_srcu(&vmdirq->irq->srcu);
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/* XXX: Potential optimization to rebalance */
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raw_spin_lock_irqsave(&list_lock, flags);
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vmdirq->irq->count--;
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raw_spin_unlock_irqrestore(&list_lock, flags);
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kfree(vmdirq);
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}
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static int vmd_msi_prepare(struct irq_domain *domain, struct device *dev,
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int nvec, msi_alloc_info_t *arg)
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{
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struct pci_dev *pdev = to_pci_dev(dev);
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struct vmd_dev *vmd = vmd_from_bus(pdev->bus);
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if (nvec > vmd->msix_count)
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return vmd->msix_count;
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memset(arg, 0, sizeof(*arg));
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return 0;
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}
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static void vmd_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
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{
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arg->desc = desc;
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}
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static struct msi_domain_ops vmd_msi_domain_ops = {
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.get_hwirq = vmd_get_hwirq,
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.msi_init = vmd_msi_init,
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.msi_free = vmd_msi_free,
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.msi_prepare = vmd_msi_prepare,
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.set_desc = vmd_set_desc,
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};
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static struct msi_domain_info vmd_msi_domain_info = {
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.flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
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MSI_FLAG_PCI_MSIX,
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.ops = &vmd_msi_domain_ops,
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.chip = &vmd_msi_controller,
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};
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static int vmd_create_irq_domain(struct vmd_dev *vmd)
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{
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struct fwnode_handle *fn;
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fn = irq_domain_alloc_named_id_fwnode("VMD-MSI", vmd->sysdata.domain);
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if (!fn)
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return -ENODEV;
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vmd->irq_domain = pci_msi_create_irq_domain(fn, &vmd_msi_domain_info,
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x86_vector_domain);
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if (!vmd->irq_domain) {
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irq_domain_free_fwnode(fn);
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return -ENODEV;
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}
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return 0;
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}
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static void vmd_remove_irq_domain(struct vmd_dev *vmd)
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{
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if (vmd->irq_domain) {
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struct fwnode_handle *fn = vmd->irq_domain->fwnode;
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irq_domain_remove(vmd->irq_domain);
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irq_domain_free_fwnode(fn);
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}
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}
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static char __iomem *vmd_cfg_addr(struct vmd_dev *vmd, struct pci_bus *bus,
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unsigned int devfn, int reg, int len)
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{
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char __iomem *addr = vmd->cfgbar +
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((bus->number - vmd->busn_start) << 20) +
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(devfn << 12) + reg;
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if ((addr - vmd->cfgbar) + len >=
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resource_size(&vmd->dev->resource[VMD_CFGBAR]))
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return NULL;
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return addr;
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}
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/*
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* CPU may deadlock if config space is not serialized on some versions of this
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* hardware, so all config space access is done under a spinlock.
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*/
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static int vmd_pci_read(struct pci_bus *bus, unsigned int devfn, int reg,
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int len, u32 *value)
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{
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struct vmd_dev *vmd = vmd_from_bus(bus);
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char __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len);
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unsigned long flags;
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int ret = 0;
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if (!addr)
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return -EFAULT;
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spin_lock_irqsave(&vmd->cfg_lock, flags);
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switch (len) {
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case 1:
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*value = readb(addr);
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break;
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case 2:
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*value = readw(addr);
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break;
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case 4:
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*value = readl(addr);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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spin_unlock_irqrestore(&vmd->cfg_lock, flags);
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return ret;
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}
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/*
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* VMD h/w converts non-posted config writes to posted memory writes. The
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* read-back in this function forces the completion so it returns only after
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* the config space was written, as expected.
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*/
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static int vmd_pci_write(struct pci_bus *bus, unsigned int devfn, int reg,
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int len, u32 value)
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{
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struct vmd_dev *vmd = vmd_from_bus(bus);
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char __iomem *addr = vmd_cfg_addr(vmd, bus, devfn, reg, len);
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unsigned long flags;
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int ret = 0;
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if (!addr)
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return -EFAULT;
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spin_lock_irqsave(&vmd->cfg_lock, flags);
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switch (len) {
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case 1:
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writeb(value, addr);
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readb(addr);
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break;
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case 2:
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writew(value, addr);
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readw(addr);
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break;
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case 4:
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writel(value, addr);
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readl(addr);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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spin_unlock_irqrestore(&vmd->cfg_lock, flags);
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return ret;
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}
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static struct pci_ops vmd_ops = {
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.read = vmd_pci_read,
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.write = vmd_pci_write,
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};
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static void vmd_attach_resources(struct vmd_dev *vmd)
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{
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vmd->dev->resource[VMD_MEMBAR1].child = &vmd->resources[1];
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vmd->dev->resource[VMD_MEMBAR2].child = &vmd->resources[2];
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}
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static void vmd_detach_resources(struct vmd_dev *vmd)
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{
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vmd->dev->resource[VMD_MEMBAR1].child = NULL;
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vmd->dev->resource[VMD_MEMBAR2].child = NULL;
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}
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/*
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* VMD domains start at 0x10000 to not clash with ACPI _SEG domains.
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* Per ACPI r6.0, sec 6.5.6, _SEG returns an integer, of which the lower
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* 16 bits are the PCI Segment Group (domain) number. Other bits are
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* currently reserved.
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*/
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static int vmd_find_free_domain(void)
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{
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int domain = 0xffff;
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struct pci_bus *bus = NULL;
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while ((bus = pci_find_next_bus(bus)) != NULL)
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domain = max_t(int, domain, pci_domain_nr(bus));
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return domain + 1;
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}
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static int vmd_get_phys_offsets(struct vmd_dev *vmd, bool native_hint,
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resource_size_t *offset1,
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resource_size_t *offset2)
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{
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struct pci_dev *dev = vmd->dev;
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u64 phys1, phys2;
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if (native_hint) {
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u32 vmlock;
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int ret;
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ret = pci_read_config_dword(dev, PCI_REG_VMLOCK, &vmlock);
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if (ret || vmlock == ~0)
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return -ENODEV;
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if (MB2_SHADOW_EN(vmlock)) {
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void __iomem *membar2;
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membar2 = pci_iomap(dev, VMD_MEMBAR2, 0);
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if (!membar2)
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return -ENOMEM;
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phys1 = readq(membar2 + MB2_SHADOW_OFFSET);
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phys2 = readq(membar2 + MB2_SHADOW_OFFSET + 8);
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pci_iounmap(dev, membar2);
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} else
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return 0;
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} else {
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/* Hypervisor-Emulated Vendor-Specific Capability */
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int pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
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u32 reg, regu;
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pci_read_config_dword(dev, pos + 4, ®);
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/* "SHDW" */
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if (pos && reg == 0x53484457) {
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pci_read_config_dword(dev, pos + 8, ®);
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pci_read_config_dword(dev, pos + 12, ®u);
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phys1 = (u64) regu << 32 | reg;
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pci_read_config_dword(dev, pos + 16, ®);
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pci_read_config_dword(dev, pos + 20, ®u);
|
|
phys2 = (u64) regu << 32 | reg;
|
|
} else
|
|
return 0;
|
|
}
|
|
|
|
*offset1 = dev->resource[VMD_MEMBAR1].start -
|
|
(phys1 & PCI_BASE_ADDRESS_MEM_MASK);
|
|
*offset2 = dev->resource[VMD_MEMBAR2].start -
|
|
(phys2 & PCI_BASE_ADDRESS_MEM_MASK);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vmd_get_bus_number_start(struct vmd_dev *vmd)
|
|
{
|
|
struct pci_dev *dev = vmd->dev;
|
|
u16 reg;
|
|
|
|
pci_read_config_word(dev, PCI_REG_VMCAP, ®);
|
|
if (BUS_RESTRICT_CAP(reg)) {
|
|
pci_read_config_word(dev, PCI_REG_VMCONFIG, ®);
|
|
|
|
switch (BUS_RESTRICT_CFG(reg)) {
|
|
case 0:
|
|
vmd->busn_start = 0;
|
|
break;
|
|
case 1:
|
|
vmd->busn_start = 128;
|
|
break;
|
|
case 2:
|
|
vmd->busn_start = 224;
|
|
break;
|
|
default:
|
|
pci_err(dev, "Unknown Bus Offset Setting (%d)\n",
|
|
BUS_RESTRICT_CFG(reg));
|
|
return -ENODEV;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static irqreturn_t vmd_irq(int irq, void *data)
|
|
{
|
|
struct vmd_irq_list *irqs = data;
|
|
struct vmd_irq *vmdirq;
|
|
int idx;
|
|
|
|
idx = srcu_read_lock(&irqs->srcu);
|
|
list_for_each_entry_rcu(vmdirq, &irqs->irq_list, node)
|
|
generic_handle_irq(vmdirq->virq);
|
|
srcu_read_unlock(&irqs->srcu, idx);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int vmd_alloc_irqs(struct vmd_dev *vmd)
|
|
{
|
|
struct pci_dev *dev = vmd->dev;
|
|
int i, err;
|
|
|
|
vmd->msix_count = pci_msix_vec_count(dev);
|
|
if (vmd->msix_count < 0)
|
|
return -ENODEV;
|
|
|
|
vmd->msix_count = pci_alloc_irq_vectors(dev, 1, vmd->msix_count,
|
|
PCI_IRQ_MSIX);
|
|
if (vmd->msix_count < 0)
|
|
return vmd->msix_count;
|
|
|
|
vmd->irqs = devm_kcalloc(&dev->dev, vmd->msix_count, sizeof(*vmd->irqs),
|
|
GFP_KERNEL);
|
|
if (!vmd->irqs)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < vmd->msix_count; i++) {
|
|
err = init_srcu_struct(&vmd->irqs[i].srcu);
|
|
if (err)
|
|
return err;
|
|
|
|
INIT_LIST_HEAD(&vmd->irqs[i].irq_list);
|
|
err = devm_request_irq(&dev->dev, pci_irq_vector(dev, i),
|
|
vmd_irq, IRQF_NO_THREAD,
|
|
"vmd", &vmd->irqs[i]);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vmd_enable_domain(struct vmd_dev *vmd, unsigned long features)
|
|
{
|
|
struct pci_sysdata *sd = &vmd->sysdata;
|
|
struct resource *res;
|
|
u32 upper_bits;
|
|
unsigned long flags;
|
|
LIST_HEAD(resources);
|
|
resource_size_t offset[2] = {0};
|
|
resource_size_t membar2_offset = 0x2000;
|
|
struct pci_bus *child;
|
|
int ret;
|
|
|
|
/*
|
|
* Shadow registers may exist in certain VMD device ids which allow
|
|
* guests to correctly assign host physical addresses to the root ports
|
|
* and child devices. These registers will either return the host value
|
|
* or 0, depending on an enable bit in the VMD device.
|
|
*/
|
|
if (features & VMD_FEAT_HAS_MEMBAR_SHADOW) {
|
|
membar2_offset = MB2_SHADOW_OFFSET + MB2_SHADOW_SIZE;
|
|
ret = vmd_get_phys_offsets(vmd, true, &offset[0], &offset[1]);
|
|
if (ret)
|
|
return ret;
|
|
} else if (features & VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP) {
|
|
ret = vmd_get_phys_offsets(vmd, false, &offset[0], &offset[1]);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Certain VMD devices may have a root port configuration option which
|
|
* limits the bus range to between 0-127, 128-255, or 224-255
|
|
*/
|
|
if (features & VMD_FEAT_HAS_BUS_RESTRICTIONS) {
|
|
ret = vmd_get_bus_number_start(vmd);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
res = &vmd->dev->resource[VMD_CFGBAR];
|
|
vmd->resources[0] = (struct resource) {
|
|
.name = "VMD CFGBAR",
|
|
.start = vmd->busn_start,
|
|
.end = vmd->busn_start + (resource_size(res) >> 20) - 1,
|
|
.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED,
|
|
};
|
|
|
|
/*
|
|
* If the window is below 4GB, clear IORESOURCE_MEM_64 so we can
|
|
* put 32-bit resources in the window.
|
|
*
|
|
* There's no hardware reason why a 64-bit window *couldn't*
|
|
* contain a 32-bit resource, but pbus_size_mem() computes the
|
|
* bridge window size assuming a 64-bit window will contain no
|
|
* 32-bit resources. __pci_assign_resource() enforces that
|
|
* artificial restriction to make sure everything will fit.
|
|
*
|
|
* The only way we could use a 64-bit non-prefetchable MEMBAR is
|
|
* if its address is <4GB so that we can convert it to a 32-bit
|
|
* resource. To be visible to the host OS, all VMD endpoints must
|
|
* be initially configured by platform BIOS, which includes setting
|
|
* up these resources. We can assume the device is configured
|
|
* according to the platform needs.
|
|
*/
|
|
res = &vmd->dev->resource[VMD_MEMBAR1];
|
|
upper_bits = upper_32_bits(res->end);
|
|
flags = res->flags & ~IORESOURCE_SIZEALIGN;
|
|
if (!upper_bits)
|
|
flags &= ~IORESOURCE_MEM_64;
|
|
vmd->resources[1] = (struct resource) {
|
|
.name = "VMD MEMBAR1",
|
|
.start = res->start,
|
|
.end = res->end,
|
|
.flags = flags,
|
|
.parent = res,
|
|
};
|
|
|
|
res = &vmd->dev->resource[VMD_MEMBAR2];
|
|
upper_bits = upper_32_bits(res->end);
|
|
flags = res->flags & ~IORESOURCE_SIZEALIGN;
|
|
if (!upper_bits)
|
|
flags &= ~IORESOURCE_MEM_64;
|
|
vmd->resources[2] = (struct resource) {
|
|
.name = "VMD MEMBAR2",
|
|
.start = res->start + membar2_offset,
|
|
.end = res->end,
|
|
.flags = flags,
|
|
.parent = res,
|
|
};
|
|
|
|
sd->vmd_dev = vmd->dev;
|
|
sd->domain = vmd_find_free_domain();
|
|
if (sd->domain < 0)
|
|
return sd->domain;
|
|
|
|
sd->node = pcibus_to_node(vmd->dev->bus);
|
|
|
|
ret = vmd_create_irq_domain(vmd);
|
|
if (ret)
|
|
return ret;
|
|
|
|
pci_add_resource(&resources, &vmd->resources[0]);
|
|
pci_add_resource_offset(&resources, &vmd->resources[1], offset[0]);
|
|
pci_add_resource_offset(&resources, &vmd->resources[2], offset[1]);
|
|
|
|
vmd->bus = pci_create_root_bus(&vmd->dev->dev, vmd->busn_start,
|
|
&vmd_ops, sd, &resources);
|
|
if (!vmd->bus) {
|
|
pci_free_resource_list(&resources);
|
|
vmd_remove_irq_domain(vmd);
|
|
return -ENODEV;
|
|
}
|
|
|
|
vmd_attach_resources(vmd);
|
|
if (vmd->irq_domain)
|
|
dev_set_msi_domain(&vmd->bus->dev, vmd->irq_domain);
|
|
|
|
pci_scan_child_bus(vmd->bus);
|
|
pci_assign_unassigned_bus_resources(vmd->bus);
|
|
|
|
/*
|
|
* VMD root buses are virtual and don't return true on pci_is_pcie()
|
|
* and will fail pcie_bus_configure_settings() early. It can instead be
|
|
* run on each of the real root ports.
|
|
*/
|
|
list_for_each_entry(child, &vmd->bus->children, node)
|
|
pcie_bus_configure_settings(child);
|
|
|
|
pci_bus_add_devices(vmd->bus);
|
|
|
|
WARN(sysfs_create_link(&vmd->dev->dev.kobj, &vmd->bus->dev.kobj,
|
|
"domain"), "Can't create symlink to domain\n");
|
|
return 0;
|
|
}
|
|
|
|
static int vmd_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
|
{
|
|
struct vmd_dev *vmd;
|
|
int err;
|
|
|
|
if (resource_size(&dev->resource[VMD_CFGBAR]) < (1 << 20))
|
|
return -ENOMEM;
|
|
|
|
vmd = devm_kzalloc(&dev->dev, sizeof(*vmd), GFP_KERNEL);
|
|
if (!vmd)
|
|
return -ENOMEM;
|
|
|
|
vmd->dev = dev;
|
|
err = pcim_enable_device(dev);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
vmd->cfgbar = pcim_iomap(dev, VMD_CFGBAR, 0);
|
|
if (!vmd->cfgbar)
|
|
return -ENOMEM;
|
|
|
|
pci_set_master(dev);
|
|
if (dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(64)) &&
|
|
dma_set_mask_and_coherent(&dev->dev, DMA_BIT_MASK(32)))
|
|
return -ENODEV;
|
|
|
|
err = vmd_alloc_irqs(vmd);
|
|
if (err)
|
|
return err;
|
|
|
|
spin_lock_init(&vmd->cfg_lock);
|
|
pci_set_drvdata(dev, vmd);
|
|
err = vmd_enable_domain(vmd, (unsigned long) id->driver_data);
|
|
if (err)
|
|
return err;
|
|
|
|
dev_info(&vmd->dev->dev, "Bound to PCI domain %04x\n",
|
|
vmd->sysdata.domain);
|
|
return 0;
|
|
}
|
|
|
|
static void vmd_cleanup_srcu(struct vmd_dev *vmd)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < vmd->msix_count; i++)
|
|
cleanup_srcu_struct(&vmd->irqs[i].srcu);
|
|
}
|
|
|
|
static void vmd_remove(struct pci_dev *dev)
|
|
{
|
|
struct vmd_dev *vmd = pci_get_drvdata(dev);
|
|
|
|
sysfs_remove_link(&vmd->dev->dev.kobj, "domain");
|
|
pci_stop_root_bus(vmd->bus);
|
|
pci_remove_root_bus(vmd->bus);
|
|
vmd_cleanup_srcu(vmd);
|
|
vmd_detach_resources(vmd);
|
|
vmd_remove_irq_domain(vmd);
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int vmd_suspend(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
struct vmd_dev *vmd = pci_get_drvdata(pdev);
|
|
int i;
|
|
|
|
for (i = 0; i < vmd->msix_count; i++)
|
|
devm_free_irq(dev, pci_irq_vector(pdev, i), &vmd->irqs[i]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int vmd_resume(struct device *dev)
|
|
{
|
|
struct pci_dev *pdev = to_pci_dev(dev);
|
|
struct vmd_dev *vmd = pci_get_drvdata(pdev);
|
|
int err, i;
|
|
|
|
for (i = 0; i < vmd->msix_count; i++) {
|
|
err = devm_request_irq(dev, pci_irq_vector(pdev, i),
|
|
vmd_irq, IRQF_NO_THREAD,
|
|
"vmd", &vmd->irqs[i]);
|
|
if (err)
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
static SIMPLE_DEV_PM_OPS(vmd_dev_pm_ops, vmd_suspend, vmd_resume);
|
|
|
|
static const struct pci_device_id vmd_ids[] = {
|
|
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_201D),
|
|
.driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP,},
|
|
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_28C0),
|
|
.driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW |
|
|
VMD_FEAT_HAS_BUS_RESTRICTIONS,},
|
|
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x467f),
|
|
.driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
|
|
VMD_FEAT_HAS_BUS_RESTRICTIONS,},
|
|
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4c3d),
|
|
.driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
|
|
VMD_FEAT_HAS_BUS_RESTRICTIONS,},
|
|
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VMD_9A0B),
|
|
.driver_data = VMD_FEAT_HAS_MEMBAR_SHADOW_VSCAP |
|
|
VMD_FEAT_HAS_BUS_RESTRICTIONS,},
|
|
{0,}
|
|
};
|
|
MODULE_DEVICE_TABLE(pci, vmd_ids);
|
|
|
|
static struct pci_driver vmd_drv = {
|
|
.name = "vmd",
|
|
.id_table = vmd_ids,
|
|
.probe = vmd_probe,
|
|
.remove = vmd_remove,
|
|
.driver = {
|
|
.pm = &vmd_dev_pm_ops,
|
|
},
|
|
};
|
|
module_pci_driver(vmd_drv);
|
|
|
|
MODULE_AUTHOR("Intel Corporation");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_VERSION("0.6");
|