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62885f59a2
This patch implements DMA support into mxs-i2c. DMA transfers are now enabled via DT. The DMA operation is enabled by default. Signed-off-by: Marek Vasut <marex@denx.de> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> [wsa: rebased to 3.6-rc7] Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
22 lines
605 B
Plaintext
22 lines
605 B
Plaintext
* Freescale MXS Inter IC (I2C) Controller
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Required properties:
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- compatible: Should be "fsl,<chip>-i2c"
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- reg: Should contain registers location and length
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- interrupts: Should contain ERROR and DMA interrupts
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- clock-frequency: Desired I2C bus clock frequency in Hz.
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Only 100000Hz and 400000Hz modes are supported.
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- fsl,i2c-dma-channel: APBX DMA channel for the I2C
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Examples:
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i2c0: i2c@80058000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx28-i2c";
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reg = <0x80058000 2000>;
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interrupts = <111 68>;
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clock-frequency = <100000>;
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fsl,i2c-dma-channel = <6>;
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};
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