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c2df0a6af1
Introduce arch_try_cmpxchg64 for 64-bit and 32-bit targets to improve code using cmpxchg64. On 64-bit targets, the generated assembly improves from: ab: 89 c8 mov %ecx,%eax ad: 48 89 4c 24 60 mov %rcx,0x60(%rsp) b2: 83 e0 fd and $0xfffffffd,%eax b5: 89 54 24 64 mov %edx,0x64(%rsp) b9: 88 44 24 60 mov %al,0x60(%rsp) bd: 48 89 c8 mov %rcx,%rax c0: c6 44 24 62 f2 movb $0xf2,0x62(%rsp) c5: 48 8b 74 24 60 mov 0x60(%rsp),%rsi ca: f0 49 0f b1 34 24 lock cmpxchg %rsi,(%r12) d0: 48 39 c1 cmp %rax,%rcx d3: 75 cf jne a4 <t+0xa4> to: b3: 89 c2 mov %eax,%edx b5: 48 89 44 24 60 mov %rax,0x60(%rsp) ba: 83 e2 fd and $0xfffffffd,%edx bd: 89 4c 24 64 mov %ecx,0x64(%rsp) c1: 88 54 24 60 mov %dl,0x60(%rsp) c5: c6 44 24 62 f2 movb $0xf2,0x62(%rsp) ca: 48 8b 54 24 60 mov 0x60(%rsp),%rdx cf: f0 48 0f b1 13 lock cmpxchg %rdx,(%rbx) d4: 75 d5 jne ab <t+0xab> where a move and a compare after cmpxchg is saved. The improvements for 32-bit targets are even more noticeable, because dual-word compare after cmpxchg8b gets eliminated. Signed-off-by: Uros Bizjak <ubizjak@gmail.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20220515184205.103089-3-ubizjak@gmail.com
137 lines
3.7 KiB
C
137 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_CMPXCHG_32_H
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#define _ASM_X86_CMPXCHG_32_H
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/*
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* Note: if you use set64_bit(), __cmpxchg64(), or their variants,
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* you need to test for the feature in boot_cpu_data.
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*/
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/*
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* CMPXCHG8B only writes to the target if we had the previous
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* value in registers, otherwise it acts as a read and gives us the
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* "new previous" value. That is why there is a loop. Preloading
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* EDX:EAX is a performance optimization: in the common case it means
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* we need only one locked operation.
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*
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* A SIMD/3DNOW!/MMX/FPU 64-bit store here would require at the very
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* least an FPU save and/or %cr0.ts manipulation.
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*
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* cmpxchg8b must be used with the lock prefix here to allow the
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* instruction to be executed atomically. We need to have the reader
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* side to see the coherent 64bit value.
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*/
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static inline void set_64bit(volatile u64 *ptr, u64 value)
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{
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u32 low = value;
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u32 high = value >> 32;
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u64 prev = *ptr;
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asm volatile("\n1:\t"
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LOCK_PREFIX "cmpxchg8b %0\n\t"
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"jnz 1b"
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: "=m" (*ptr), "+A" (prev)
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: "b" (low), "c" (high)
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: "memory");
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}
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#ifdef CONFIG_X86_CMPXCHG64
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#define arch_cmpxchg64(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg64((ptr), (unsigned long long)(o), \
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(unsigned long long)(n)))
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#define arch_cmpxchg64_local(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg64_local((ptr), (unsigned long long)(o), \
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(unsigned long long)(n)))
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#define arch_try_cmpxchg64(ptr, po, n) \
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__try_cmpxchg64((ptr), (unsigned long long *)(po), \
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(unsigned long long)(n))
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#endif
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static inline u64 __cmpxchg64(volatile u64 *ptr, u64 old, u64 new)
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{
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u64 prev;
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asm volatile(LOCK_PREFIX "cmpxchg8b %1"
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: "=A" (prev),
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"+m" (*ptr)
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: "b" ((u32)new),
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"c" ((u32)(new >> 32)),
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"0" (old)
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: "memory");
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return prev;
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}
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static inline u64 __cmpxchg64_local(volatile u64 *ptr, u64 old, u64 new)
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{
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u64 prev;
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asm volatile("cmpxchg8b %1"
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: "=A" (prev),
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"+m" (*ptr)
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: "b" ((u32)new),
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"c" ((u32)(new >> 32)),
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"0" (old)
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: "memory");
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return prev;
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}
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static inline bool __try_cmpxchg64(volatile u64 *ptr, u64 *pold, u64 new)
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{
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bool success;
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u64 old = *pold;
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asm volatile(LOCK_PREFIX "cmpxchg8b %[ptr]"
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CC_SET(z)
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: CC_OUT(z) (success),
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[ptr] "+m" (*ptr),
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"+A" (old)
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: "b" ((u32)new),
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"c" ((u32)(new >> 32))
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: "memory");
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if (unlikely(!success))
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*pold = old;
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return success;
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}
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#ifndef CONFIG_X86_CMPXCHG64
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/*
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* Building a kernel capable running on 80386 and 80486. It may be necessary
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* to simulate the cmpxchg8b on the 80386 and 80486 CPU.
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*/
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#define arch_cmpxchg64(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) __ret; \
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__typeof__(*(ptr)) __old = (o); \
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__typeof__(*(ptr)) __new = (n); \
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alternative_io(LOCK_PREFIX_HERE \
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"call cmpxchg8b_emu", \
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"lock; cmpxchg8b (%%esi)" , \
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X86_FEATURE_CX8, \
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"=A" (__ret), \
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"S" ((ptr)), "0" (__old), \
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"b" ((unsigned int)__new), \
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"c" ((unsigned int)(__new>>32)) \
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: "memory"); \
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__ret; })
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#define arch_cmpxchg64_local(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) __ret; \
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__typeof__(*(ptr)) __old = (o); \
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__typeof__(*(ptr)) __new = (n); \
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alternative_io("call cmpxchg8b_emu", \
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"cmpxchg8b (%%esi)" , \
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X86_FEATURE_CX8, \
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"=A" (__ret), \
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"S" ((ptr)), "0" (__old), \
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"b" ((unsigned int)__new), \
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"c" ((unsigned int)(__new>>32)) \
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: "memory"); \
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__ret; })
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#endif
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#define system_has_cmpxchg_double() boot_cpu_has(X86_FEATURE_CX8)
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#endif /* _ASM_X86_CMPXCHG_32_H */
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