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930bff8822
IP28 needs special treatment to avoid speculative accesses. gcc takes care for .c code, but for assembly code we need to do it manually. This is taken from Peter Fuersts IP28 patches. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
567 lines
13 KiB
ArmAsm
567 lines
13 KiB
ArmAsm
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Unified implementation of memcpy, memmove and the __copy_user backend.
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*
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* Copyright (C) 1998, 99, 2000, 01, 2002 Ralf Baechle (ralf@gnu.org)
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* Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc.
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* Copyright (C) 2002 Broadcom, Inc.
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* memcpy/copy_user author: Mark Vandevoorde
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* Copyright (C) 2007 Maciej W. Rozycki
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*
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* Mnemonic names for arguments to memcpy/__copy_user
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*/
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/*
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* Hack to resolve longstanding prefetch issue
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*
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* Prefetching may be fatal on some systems if we're prefetching beyond the
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* end of memory on some systems. It's also a seriously bad idea on non
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* dma-coherent systems.
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*/
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#if !defined(CONFIG_DMA_COHERENT) || !defined(CONFIG_DMA_IP27)
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#undef CONFIG_CPU_HAS_PREFETCH
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#endif
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#ifdef CONFIG_MIPS_MALTA
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#undef CONFIG_CPU_HAS_PREFETCH
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#endif
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/regdef.h>
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#define dst a0
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#define src a1
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#define len a2
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/*
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* Spec
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*
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* memcpy copies len bytes from src to dst and sets v0 to dst.
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* It assumes that
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* - src and dst don't overlap
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* - src is readable
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* - dst is writable
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* memcpy uses the standard calling convention
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*
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* __copy_user copies up to len bytes from src to dst and sets a2 (len) to
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* the number of uncopied bytes due to an exception caused by a read or write.
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* __copy_user assumes that src and dst don't overlap, and that the call is
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* implementing one of the following:
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* copy_to_user
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* - src is readable (no exceptions when reading src)
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* copy_from_user
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* - dst is writable (no exceptions when writing dst)
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* __copy_user uses a non-standard calling convention; see
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* include/asm-mips/uaccess.h
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*
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* When an exception happens on a load, the handler must
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# ensure that all of the destination buffer is overwritten to prevent
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* leaking information to user mode programs.
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*/
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/*
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* Implementation
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*/
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/*
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* The exception handler for loads requires that:
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* 1- AT contain the address of the byte just past the end of the source
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* of the copy,
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* 2- src_entry <= src < AT, and
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* 3- (dst - src) == (dst_entry - src_entry),
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* The _entry suffix denotes values when __copy_user was called.
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*
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* (1) is set up up by uaccess.h and maintained by not writing AT in copy_user
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* (2) is met by incrementing src by the number of bytes copied
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* (3) is met by not doing loads between a pair of increments of dst and src
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*
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* The exception handlers for stores adjust len (if necessary) and return.
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* These handlers do not need to overwrite any data.
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*
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* For __rmemcpy and memmove an exception is always a kernel bug, therefore
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* they're not protected.
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*/
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#define EXC(inst_reg,addr,handler) \
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9: inst_reg, addr; \
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.section __ex_table,"a"; \
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PTR 9b, handler; \
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.previous
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/*
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* Only on the 64-bit kernel we can made use of 64-bit registers.
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*/
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#ifdef CONFIG_64BIT
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#define USE_DOUBLE
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#endif
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#ifdef USE_DOUBLE
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#define LOAD ld
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#define LOADL ldl
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#define LOADR ldr
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#define STOREL sdl
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#define STORER sdr
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#define STORE sd
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#define ADD daddu
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#define SUB dsubu
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#define SRL dsrl
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#define SRA dsra
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#define SLL dsll
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#define SLLV dsllv
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#define SRLV dsrlv
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#define NBYTES 8
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#define LOG_NBYTES 3
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/*
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* As we are sharing code base with the mips32 tree (which use the o32 ABI
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* register definitions). We need to redefine the register definitions from
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* the n64 ABI register naming to the o32 ABI register naming.
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*/
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#undef t0
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#undef t1
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#undef t2
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#undef t3
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#define t0 $8
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#define t1 $9
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#define t2 $10
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#define t3 $11
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#define t4 $12
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#define t5 $13
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#define t6 $14
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#define t7 $15
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#else
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#define LOAD lw
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#define LOADL lwl
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#define LOADR lwr
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#define STOREL swl
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#define STORER swr
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#define STORE sw
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#define ADD addu
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#define SUB subu
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#define SRL srl
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#define SLL sll
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#define SRA sra
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#define SLLV sllv
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#define SRLV srlv
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#define NBYTES 4
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#define LOG_NBYTES 2
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#endif /* USE_DOUBLE */
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#ifdef CONFIG_CPU_LITTLE_ENDIAN
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#define LDFIRST LOADR
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#define LDREST LOADL
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#define STFIRST STORER
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#define STREST STOREL
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#define SHIFT_DISCARD SLLV
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#else
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#define LDFIRST LOADL
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#define LDREST LOADR
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#define STFIRST STOREL
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#define STREST STORER
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#define SHIFT_DISCARD SRLV
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#endif
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#define FIRST(unit) ((unit)*NBYTES)
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#define REST(unit) (FIRST(unit)+NBYTES-1)
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#define UNIT(unit) FIRST(unit)
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#define ADDRMASK (NBYTES-1)
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.text
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.set noreorder
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#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
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.set noat
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#else
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.set at=v1
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#endif
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/*
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* A combined memcpy/__copy_user
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* __copy_user sets len to 0 for success; else to an upper bound of
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* the number of uncopied bytes.
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* memcpy sets v0 to dst.
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*/
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.align 5
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LEAF(memcpy) /* a0=dst a1=src a2=len */
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move v0, dst /* return value */
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__memcpy:
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FEXPORT(__copy_user)
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/*
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* Note: dst & src may be unaligned, len may be 0
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* Temps
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*/
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#define rem t8
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R10KCBARRIER(0(ra))
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/*
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* The "issue break"s below are very approximate.
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* Issue delays for dcache fills will perturb the schedule, as will
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* load queue full replay traps, etc.
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*
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* If len < NBYTES use byte operations.
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*/
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PREF( 0, 0(src) )
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PREF( 1, 0(dst) )
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sltu t2, len, NBYTES
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and t1, dst, ADDRMASK
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PREF( 0, 1*32(src) )
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PREF( 1, 1*32(dst) )
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bnez t2, copy_bytes_checklen
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and t0, src, ADDRMASK
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PREF( 0, 2*32(src) )
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PREF( 1, 2*32(dst) )
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bnez t1, dst_unaligned
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nop
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bnez t0, src_unaligned_dst_aligned
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/*
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* use delay slot for fall-through
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* src and dst are aligned; need to compute rem
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*/
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both_aligned:
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SRL t0, len, LOG_NBYTES+3 # +3 for 8 units/iter
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beqz t0, cleanup_both_aligned # len < 8*NBYTES
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and rem, len, (8*NBYTES-1) # rem = len % (8*NBYTES)
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PREF( 0, 3*32(src) )
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PREF( 1, 3*32(dst) )
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.align 4
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1:
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R10KCBARRIER(0(ra))
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EXC( LOAD t0, UNIT(0)(src), l_exc)
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EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
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EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
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EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
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SUB len, len, 8*NBYTES
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EXC( LOAD t4, UNIT(4)(src), l_exc_copy)
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EXC( LOAD t7, UNIT(5)(src), l_exc_copy)
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EXC( STORE t0, UNIT(0)(dst), s_exc_p8u)
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EXC( STORE t1, UNIT(1)(dst), s_exc_p7u)
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EXC( LOAD t0, UNIT(6)(src), l_exc_copy)
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EXC( LOAD t1, UNIT(7)(src), l_exc_copy)
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ADD src, src, 8*NBYTES
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ADD dst, dst, 8*NBYTES
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EXC( STORE t2, UNIT(-6)(dst), s_exc_p6u)
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EXC( STORE t3, UNIT(-5)(dst), s_exc_p5u)
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EXC( STORE t4, UNIT(-4)(dst), s_exc_p4u)
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EXC( STORE t7, UNIT(-3)(dst), s_exc_p3u)
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EXC( STORE t0, UNIT(-2)(dst), s_exc_p2u)
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EXC( STORE t1, UNIT(-1)(dst), s_exc_p1u)
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PREF( 0, 8*32(src) )
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PREF( 1, 8*32(dst) )
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bne len, rem, 1b
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nop
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/*
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* len == rem == the number of bytes left to copy < 8*NBYTES
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*/
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cleanup_both_aligned:
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beqz len, done
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sltu t0, len, 4*NBYTES
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bnez t0, less_than_4units
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and rem, len, (NBYTES-1) # rem = len % NBYTES
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/*
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* len >= 4*NBYTES
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*/
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EXC( LOAD t0, UNIT(0)(src), l_exc)
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EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
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EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
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EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
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SUB len, len, 4*NBYTES
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ADD src, src, 4*NBYTES
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R10KCBARRIER(0(ra))
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EXC( STORE t0, UNIT(0)(dst), s_exc_p4u)
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EXC( STORE t1, UNIT(1)(dst), s_exc_p3u)
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EXC( STORE t2, UNIT(2)(dst), s_exc_p2u)
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EXC( STORE t3, UNIT(3)(dst), s_exc_p1u)
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.set reorder /* DADDI_WAR */
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ADD dst, dst, 4*NBYTES
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beqz len, done
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.set noreorder
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less_than_4units:
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/*
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* rem = len % NBYTES
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*/
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beq rem, len, copy_bytes
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nop
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1:
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R10KCBARRIER(0(ra))
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EXC( LOAD t0, 0(src), l_exc)
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ADD src, src, NBYTES
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SUB len, len, NBYTES
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EXC( STORE t0, 0(dst), s_exc_p1u)
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.set reorder /* DADDI_WAR */
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ADD dst, dst, NBYTES
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bne rem, len, 1b
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.set noreorder
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/*
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* src and dst are aligned, need to copy rem bytes (rem < NBYTES)
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* A loop would do only a byte at a time with possible branch
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* mispredicts. Can't do an explicit LOAD dst,mask,or,STORE
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* because can't assume read-access to dst. Instead, use
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* STREST dst, which doesn't require read access to dst.
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*
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* This code should perform better than a simple loop on modern,
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* wide-issue mips processors because the code has fewer branches and
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* more instruction-level parallelism.
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*/
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#define bits t2
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beqz len, done
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ADD t1, dst, len # t1 is just past last byte of dst
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li bits, 8*NBYTES
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SLL rem, len, 3 # rem = number of bits to keep
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EXC( LOAD t0, 0(src), l_exc)
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SUB bits, bits, rem # bits = number of bits to discard
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SHIFT_DISCARD t0, t0, bits
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EXC( STREST t0, -1(t1), s_exc)
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jr ra
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move len, zero
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dst_unaligned:
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/*
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* dst is unaligned
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* t0 = src & ADDRMASK
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* t1 = dst & ADDRMASK; T1 > 0
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* len >= NBYTES
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*
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* Copy enough bytes to align dst
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* Set match = (src and dst have same alignment)
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*/
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#define match rem
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EXC( LDFIRST t3, FIRST(0)(src), l_exc)
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ADD t2, zero, NBYTES
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EXC( LDREST t3, REST(0)(src), l_exc_copy)
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SUB t2, t2, t1 # t2 = number of bytes copied
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xor match, t0, t1
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R10KCBARRIER(0(ra))
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EXC( STFIRST t3, FIRST(0)(dst), s_exc)
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beq len, t2, done
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SUB len, len, t2
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ADD dst, dst, t2
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beqz match, both_aligned
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ADD src, src, t2
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src_unaligned_dst_aligned:
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SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
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PREF( 0, 3*32(src) )
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beqz t0, cleanup_src_unaligned
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and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES
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PREF( 1, 3*32(dst) )
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1:
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/*
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* Avoid consecutive LD*'s to the same register since some mips
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* implementations can't issue them in the same cycle.
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* It's OK to load FIRST(N+1) before REST(N) because the two addresses
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* are to the same unit (unless src is aligned, but it's not).
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*/
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R10KCBARRIER(0(ra))
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EXC( LDFIRST t0, FIRST(0)(src), l_exc)
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EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy)
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SUB len, len, 4*NBYTES
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EXC( LDREST t0, REST(0)(src), l_exc_copy)
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EXC( LDREST t1, REST(1)(src), l_exc_copy)
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EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy)
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EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy)
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EXC( LDREST t2, REST(2)(src), l_exc_copy)
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EXC( LDREST t3, REST(3)(src), l_exc_copy)
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PREF( 0, 9*32(src) ) # 0 is PREF_LOAD (not streamed)
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ADD src, src, 4*NBYTES
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#ifdef CONFIG_CPU_SB1
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nop # improves slotting
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#endif
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EXC( STORE t0, UNIT(0)(dst), s_exc_p4u)
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EXC( STORE t1, UNIT(1)(dst), s_exc_p3u)
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EXC( STORE t2, UNIT(2)(dst), s_exc_p2u)
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EXC( STORE t3, UNIT(3)(dst), s_exc_p1u)
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PREF( 1, 9*32(dst) ) # 1 is PREF_STORE (not streamed)
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.set reorder /* DADDI_WAR */
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ADD dst, dst, 4*NBYTES
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bne len, rem, 1b
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.set noreorder
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cleanup_src_unaligned:
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beqz len, done
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and rem, len, NBYTES-1 # rem = len % NBYTES
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beq rem, len, copy_bytes
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nop
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1:
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R10KCBARRIER(0(ra))
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EXC( LDFIRST t0, FIRST(0)(src), l_exc)
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EXC( LDREST t0, REST(0)(src), l_exc_copy)
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ADD src, src, NBYTES
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SUB len, len, NBYTES
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EXC( STORE t0, 0(dst), s_exc_p1u)
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.set reorder /* DADDI_WAR */
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ADD dst, dst, NBYTES
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bne len, rem, 1b
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.set noreorder
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copy_bytes_checklen:
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beqz len, done
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nop
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copy_bytes:
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/* 0 < len < NBYTES */
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R10KCBARRIER(0(ra))
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#define COPY_BYTE(N) \
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EXC( lb t0, N(src), l_exc); \
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SUB len, len, 1; \
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beqz len, done; \
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EXC( sb t0, N(dst), s_exc_p1)
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COPY_BYTE(0)
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COPY_BYTE(1)
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#ifdef USE_DOUBLE
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COPY_BYTE(2)
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COPY_BYTE(3)
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COPY_BYTE(4)
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COPY_BYTE(5)
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#endif
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EXC( lb t0, NBYTES-2(src), l_exc)
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SUB len, len, 1
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jr ra
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EXC( sb t0, NBYTES-2(dst), s_exc_p1)
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done:
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jr ra
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nop
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END(memcpy)
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l_exc_copy:
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/*
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* Copy bytes from src until faulting load address (or until a
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* lb faults)
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*
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* When reached by a faulting LDFIRST/LDREST, THREAD_BUADDR($28)
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* may be more than a byte beyond the last address.
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* Hence, the lb below may get an exception.
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*
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* Assumes src < THREAD_BUADDR($28)
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*/
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LOAD t0, TI_TASK($28)
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nop
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LOAD t0, THREAD_BUADDR(t0)
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1:
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EXC( lb t1, 0(src), l_exc)
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ADD src, src, 1
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sb t1, 0(dst) # can't fault -- we're copy_from_user
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.set reorder /* DADDI_WAR */
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ADD dst, dst, 1
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bne src, t0, 1b
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.set noreorder
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l_exc:
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LOAD t0, TI_TASK($28)
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nop
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LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address
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nop
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SUB len, AT, t0 # len number of uncopied bytes
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/*
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* Here's where we rely on src and dst being incremented in tandem,
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* See (3) above.
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* dst += (fault addr - src) to put dst at first byte to clear
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*/
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ADD dst, t0 # compute start address in a1
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SUB dst, src
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/*
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* Clear len bytes starting at dst. Can't call __bzero because it
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* might modify len. An inefficient loop for these rare times...
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*/
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.set reorder /* DADDI_WAR */
|
|
SUB src, len, 1
|
|
beqz len, done
|
|
.set noreorder
|
|
1: sb zero, 0(dst)
|
|
ADD dst, dst, 1
|
|
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
|
|
bnez src, 1b
|
|
SUB src, src, 1
|
|
#else
|
|
.set push
|
|
.set noat
|
|
li v1, 1
|
|
bnez src, 1b
|
|
SUB src, src, v1
|
|
.set pop
|
|
#endif
|
|
jr ra
|
|
nop
|
|
|
|
|
|
#define SEXC(n) \
|
|
.set reorder; /* DADDI_WAR */ \
|
|
s_exc_p ## n ## u: \
|
|
ADD len, len, n*NBYTES; \
|
|
jr ra; \
|
|
.set noreorder
|
|
|
|
SEXC(8)
|
|
SEXC(7)
|
|
SEXC(6)
|
|
SEXC(5)
|
|
SEXC(4)
|
|
SEXC(3)
|
|
SEXC(2)
|
|
SEXC(1)
|
|
|
|
s_exc_p1:
|
|
.set reorder /* DADDI_WAR */
|
|
ADD len, len, 1
|
|
jr ra
|
|
.set noreorder
|
|
s_exc:
|
|
jr ra
|
|
nop
|
|
|
|
.align 5
|
|
LEAF(memmove)
|
|
ADD t0, a0, a2
|
|
ADD t1, a1, a2
|
|
sltu t0, a1, t0 # dst + len <= src -> memcpy
|
|
sltu t1, a0, t1 # dst >= src + len -> memcpy
|
|
and t0, t1
|
|
beqz t0, __memcpy
|
|
move v0, a0 /* return value */
|
|
beqz a2, r_out
|
|
END(memmove)
|
|
|
|
/* fall through to __rmemcpy */
|
|
LEAF(__rmemcpy) /* a0=dst a1=src a2=len */
|
|
sltu t0, a1, a0
|
|
beqz t0, r_end_bytes_up # src >= dst
|
|
nop
|
|
ADD a0, a2 # dst = dst + len
|
|
ADD a1, a2 # src = src + len
|
|
|
|
r_end_bytes:
|
|
R10KCBARRIER(0(ra))
|
|
lb t0, -1(a1)
|
|
SUB a2, a2, 0x1
|
|
sb t0, -1(a0)
|
|
SUB a1, a1, 0x1
|
|
.set reorder /* DADDI_WAR */
|
|
SUB a0, a0, 0x1
|
|
bnez a2, r_end_bytes
|
|
.set noreorder
|
|
|
|
r_out:
|
|
jr ra
|
|
move a2, zero
|
|
|
|
r_end_bytes_up:
|
|
R10KCBARRIER(0(ra))
|
|
lb t0, (a1)
|
|
SUB a2, a2, 0x1
|
|
sb t0, (a0)
|
|
ADD a1, a1, 0x1
|
|
.set reorder /* DADDI_WAR */
|
|
ADD a0, a0, 0x1
|
|
bnez a2, r_end_bytes_up
|
|
.set noreorder
|
|
|
|
jr ra
|
|
move a2, zero
|
|
END(__rmemcpy)
|