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c22437b78e
Migrate netx driver to the new 'set-state' interface provided by clockevents core, the earlier 'set-mode' interface is marked obsolete now. This also enables us to implement callbacks for new states of clockevent devices, for example: ONESHOT_STOPPED. We aren't writing zero twice on the control register for shutdown or resume state now. Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
154 lines
4.2 KiB
C
154 lines
4.2 KiB
C
/*
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* arch/arm/mach-netx/time.c
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*
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* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/mach/time.h>
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#include <mach/netx-regs.h>
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#define NETX_CLOCK_FREQ 100000000
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#define NETX_LATCH DIV_ROUND_CLOSEST(NETX_CLOCK_FREQ, HZ)
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#define TIMER_CLOCKEVENT 0
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#define TIMER_CLOCKSOURCE 1
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static inline void timer_shutdown(struct clock_event_device *evt)
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{
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/* disable timer */
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writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));
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}
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static int netx_shutdown(struct clock_event_device *evt)
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{
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timer_shutdown(evt);
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return 0;
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}
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static int netx_set_oneshot(struct clock_event_device *evt)
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{
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u32 tmode = NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN;
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timer_shutdown(evt);
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writel(0, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
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writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));
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return 0;
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}
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static int netx_set_periodic(struct clock_event_device *evt)
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{
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u32 tmode = NETX_GPIO_COUNTER_CTRL_RST_EN |
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NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN;
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timer_shutdown(evt);
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writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT));
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writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT));
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return 0;
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}
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static int netx_set_next_event(unsigned long evt,
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struct clock_event_device *clk)
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{
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writel(0 - evt, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKEVENT));
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return 0;
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}
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static struct clock_event_device netx_clockevent = {
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.name = "netx-timer" __stringify(TIMER_CLOCKEVENT),
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_next_event = netx_set_next_event,
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.set_state_shutdown = netx_shutdown,
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.set_state_periodic = netx_set_periodic,
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.set_state_oneshot = netx_set_oneshot,
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.tick_resume = netx_shutdown,
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};
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t
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netx_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &netx_clockevent;
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/* acknowledge interrupt */
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writel(COUNTER_BIT(0), NETX_GPIO_IRQ);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction netx_timer_irq = {
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.name = "NetX Timer Tick",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = netx_timer_interrupt,
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};
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/*
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* Set up timer interrupt
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*/
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void __init netx_timer_init(void)
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{
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/* disable timer initially */
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writel(0, NETX_GPIO_COUNTER_CTRL(0));
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/* Reset the timer value to zero */
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writel(0, NETX_GPIO_COUNTER_CURRENT(0));
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writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(0));
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/* acknowledge interrupt */
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writel(COUNTER_BIT(0), NETX_GPIO_IRQ);
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/* Enable the interrupt in the specific timer
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* register and start timer
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*/
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writel(COUNTER_BIT(0), NETX_GPIO_IRQ_ENABLE);
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writel(NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN,
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NETX_GPIO_COUNTER_CTRL(0));
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setup_irq(NETX_IRQ_TIMER0, &netx_timer_irq);
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/* Setup timer one for clocksource */
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writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
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writel(0, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE));
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writel(0xffffffff, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKSOURCE));
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writel(NETX_GPIO_COUNTER_CTRL_RUN,
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NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
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clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE),
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"netx_timer", NETX_CLOCK_FREQ, 200, 32, clocksource_mmio_readl_up);
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/* with max_delta_ns >= delta2ns(0x800) the system currently runs fine.
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* Adding some safety ... */
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netx_clockevent.cpumask = cpumask_of(0);
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clockevents_config_and_register(&netx_clockevent, NETX_CLOCK_FREQ,
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0xa00, 0xfffffffe);
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}
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