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ARMv6 and greater introduced a new instruction ("bx") which can be used
to return from function calls. Recent CPUs perform better when the
"bx lr" instruction is used rather than the "mov pc, lr" instruction,
and this sequence is strongly recommended to be used by the ARM
architecture manual (section A.4.1.1).
We provide a new macro "ret" with all its variants for the condition
code which will resolve to the appropriate instruction.
Rather than doing this piecemeal, and miss some instances, change all
the "mov pc" instances to use the new macro, with the exception of
the "movs" instruction and the kprobes code. This allows us to detect
the "mov pc, lr" case and fix it up - and also gives us the possibility
of deploying this for other registers depending on the CPU selection.
Reported-by: Will Deacon <will.deacon@arm.com>
Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S
Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood
Tested-by: Shawn Guo <shawn.guo@freescale.com>
Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385
Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci
Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen
Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M
Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
50 lines
1.2 KiB
ArmAsm
50 lines
1.2 KiB
ArmAsm
/*
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* linux/arch/arm/kernel/fiqasm.S
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*
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* Derived from code originally in linux/arch/arm/kernel/fiq.c:
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*
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* Copyright (C) 1998 Russell King
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* Copyright (C) 1998, 1999 Phil Blundell
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* Copyright (C) 2011, Linaro Limited
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*
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* FIQ support written by Philip Blundell <philb@gnu.org>, 1998.
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*
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* FIQ support re-written by Russell King to be more generic
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*
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* v7/Thumb-2 compatibility modifications by Linaro Limited, 2011.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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/*
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* Taking an interrupt in FIQ mode is death, so both these functions
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* disable irqs for the duration.
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*/
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ENTRY(__set_fiq_regs)
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mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
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mrs r1, cpsr
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msr cpsr_c, r2 @ select FIQ mode
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mov r0, r0 @ avoid hazard prior to ARMv4
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ldmia r0!, {r8 - r12}
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ldr sp, [r0], #4
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ldr lr, [r0]
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msr cpsr_c, r1 @ return to SVC mode
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mov r0, r0 @ avoid hazard prior to ARMv4
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ret lr
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ENDPROC(__set_fiq_regs)
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ENTRY(__get_fiq_regs)
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mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
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mrs r1, cpsr
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msr cpsr_c, r2 @ select FIQ mode
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mov r0, r0 @ avoid hazard prior to ARMv4
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stmia r0!, {r8 - r12}
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str sp, [r0], #4
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str lr, [r0]
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msr cpsr_c, r1 @ return to SVC mode
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mov r0, r0 @ avoid hazard prior to ARMv4
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ret lr
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ENDPROC(__get_fiq_regs)
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